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Volumn , Issue , 2008, Pages 1632-1635

A novel DPS integrator for fast CMOS imagers

Author keywords

[No Author keywords available]

Indexed keywords

CMOS IMAGERS; INTERNATIONAL SYMPOSIUM; SWITCHING DEVICES;

EID: 51749099371     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2008.4541747     Document Type: Conference Paper
Times cited : (10)

References (7)
  • 2
    • 33645134141 scopus 로고    scopus 로고
    • A 1.2-V 0.25-μm Clock Ouptut Pixel Architecture With Wide Dynamic Range and Self-Offset Cancellation
    • Apr
    • C.-H. Lai, Y.-C. King, and S.-Y. Huang, "A 1.2-V 0.25-μm Clock Ouptut Pixel Architecture With Wide Dynamic Range and Self-Offset Cancellation," IEEE Sensors Journal, vol. 6, no. 2, pp. 398-405, Apr 2006.
    • (2006) IEEE Sensors Journal , vol.6 , Issue.2 , pp. 398-405
    • Lai, C.-H.1    King, Y.-C.2    Huang, S.-Y.3
  • 3
    • 0035334375 scopus 로고    scopus 로고
    • A Low-Power Low-Noise Ultrawide-Dynamic-Range CMOS Imager with Pixel-Parallel A/D Conversion
    • May
    • L. G. McIlrath, "A Low-Power Low-Noise Ultrawide-Dynamic-Range CMOS Imager with Pixel-Parallel A/D Conversion," IEEE Journal of Solid State Circuits, vol. 36, no. 5, pp. 846-853, May 2001.
    • (2001) IEEE Journal of Solid State Circuits , vol.36 , Issue.5 , pp. 846-853
    • McIlrath, L.G.1
  • 5
    • 0242573716 scopus 로고    scopus 로고
    • A Comparative Study of Access Topologies for Chip-Level Address-Event Communication Channels
    • Sep
    • E. Culurciello and A. G. Andreou, "A Comparative Study of Access Topologies for Chip-Level Address-Event Communication Channels," IEEE Transactions on Neural Networks, vol. 14, no. 5, pp. 1266-1277, Sep 2003.
    • (2003) IEEE Transactions on Neural Networks , vol.14 , Issue.5 , pp. 1266-1277
    • Culurciello, E.1    Andreou, A.G.2
  • 6
    • 33645234847 scopus 로고    scopus 로고
    • Area-Efficient Correlated Double Sampling Scheme with Single Sampling Capacitor for CMOS Image Sensors
    • Mar
    • S.-W. Han and E. Yon, "Area-Efficient Correlated Double Sampling Scheme with Single Sampling Capacitor for CMOS Image Sensors," IEE Electronics Letters, vol. 42, no. 6, pp. 335-337, Mar 2006.
    • (2006) IEE Electronics Letters , vol.42 , Issue.6 , pp. 335-337
    • Han, S.-W.1    Yon, E.2
  • 7
    • 0029342165 scopus 로고
    • An Analytical MOS Transistor Model Valid in All Regions of Operation and Dedicated to Low-Voltage and Low-Current Applications
    • Kluwer Academic Publishers
    • C. C. Enz, F. Krummenacher, and E. A. Vittoz, "An Analytical MOS Transistor Model Valid in All Regions of Operation and Dedicated to Low-Voltage and Low-Current Applications," Journal of Analog Integrated Circuits and Signal Processing, Kluwer Academic Publishers, vol. 8, no. 1, pp. 83-114, 1995.
    • (1995) Journal of Analog Integrated Circuits and Signal Processing , vol.8 , Issue.1 , pp. 83-114
    • Enz, C.C.1    Krummenacher, F.2    Vittoz, E.A.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.