A parallel hardware architecture for connected component labeling based on fast label merging

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn , Issue , 2008, Pages 144-149

  Flatt, Holger ^a   Blume, Steffen ^a   Hesselbarth, Sebastian ^a   Schünemann, Torsten ^a   Pirsch, Peter ^a  

^a LEIBNIZ UNIVERSITY HANNOVER   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); IMAGE PROCESSING; LABELS; MERGING; TELECOMMUNICATION NETWORKS;

APPLICATION-SPECIFIC SYSTEMS; INTERNATIONAL CONFERENCES; LABEL MERGING;

ARCHITECTURE;

EID: 51649094584     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2008.4580169     Document Type: Conference Paper

References (18)

1. F. Chang, C. Chen, and C. Lu. A linear-time component-labeling algorithm using contour tracing technique. Computer Vision and Image Understanding, 93(2):206-220, 2004.
2. A. Choudhary and R. Thakur. Evaluation of connected component labeling algorithms on shared and distributed memory multiprocessors. Parallel Processing Symposium, 1992. Proceedings., Sixth International, pages 362-365, 1992.
3. M. Ercan and Y.-F. Fung. Connected component labeling on a one dimensional DSP array. TENCON 99. Proceedings of the IEEE Region 10 Conference, 2:1299-1302, 1999.
4. H. Flatt, S. Hesselbarth, S. Flügel, and P. Pirsch. A Modular Coprocessor Architecture for Embedded Real-Time Image and Video Signal Processing. In S. V. et al. (Eds.), editor, SAMOS 2007, LNCS 4599, pages 241-250, 2007.
5. S.-D. Jean, C.-M. Liu, C.-C. Chang, and Z. Chen. A new algorithm and its VLSI architecture design for connected component labeling. Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on, 2:565-568, 1994.
6. R. Lumia, L. Shapiro, and O. Zuniga. A new connected components algorithm for virtual memory computers. Computer Vision, Graphics, and Image Processing, 22(2):287-300, 1983.
7. E. Mozef, S. Weber, J. Jaber, and E. Tisserand. Parallel architecture dedicated to connected component analysis. In S.Weber, editor, Pattern Recognition, 1996., Proceedings of the 13th International Conference on, volume 4, pages 699-703 vol.4, 1996.
8. C. Nicol. A systolic approach for real time connected component labeling. Computer Vision and Image Understanding, 61(1):17-31, 1995.
9. J. Park, C. Looney, and H. Chen. Fast Connected Component Labeling Algorithm Using A Divide and Conquer Technique. Proc of the ISCA 15th International Conferenee on Computers and Their Applications, New Orleans, LA, 2000.
10. ProDesign GmbH. Products, CHIPit Gold Edition Pro, http://www.uchipit. com.
11. N. Ranganathan, R. Mehrotra, and S. Subramanian. A high speed systolic architecture for labeling connected components in an image. Systems, Man and Cybernetics, IEEE Transactions on, 25(3):415-423, 1995.
12. A. Rosenfeld and J. L. Pfaltz. Sequential Operations in Digital Picture Processing. J. ACM, 13(4):471-494, Oct 1966.
13. T. Schünemann. Konzeption und VHDL-Implementierung einer Labeling-Einheit für eine FPGA-basierte Coprozessorarchitektur. Semester Project, Leibniz Universität Hannover (in German), Nov 2007.
14. Y. Shin, R. Sridhar, V. Demjanenko, and S. Palumbo, P.W.and Srihari. A special-purpose content addressable memory chip for real-time image processing. Solid-State Circuits, IEEE Journal of, 27(5):737-744, 1992.
15. K. Suzuki, I. Horiba, and N. Sugie. Linear-time connected-component labeling based on sequential local operations. Computer Vision and Image Understanding, 89(1):1-23, 2003.
16. K.-B. Wang, T.-L. Chia, Z. Chen, and D.-C. Lou. Parallel Execution of a Connected Component Labeling Operation on a Linear Array Architecture. In Journal of Information Science and Engineering, volume 19, no. 2, pages 353-370, 2003.
17. K. Wu, E. Otoo, and K. Suzuki. Two Strategies to Speed up Connected Component Labeling Algorithms. Technical Report LBNL-59102, LBNL, 2005.
18. S.-W. Yang, M.-H. Sheu, H.-H. Wu, H.-E. Chien, P.-K. Weng, and Y.-Y. Wu. VLSI architecture design for a fast parallel label assignment in binary image. Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on, 3:2393-2396, 2005.