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Volumn , Issue , 2007, Pages 65-67

Evolvable reconfigurable hardare framework for edge detection

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); GENETIC ALGORITHMS; IMAGE PROCESSING;

EID: 51449105041     PISSN: 15483746     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MWSCAS.2007.4488542     Document Type: Conference Paper
Times cited : (3)

References (12)
  • 7
    • 0035341885 scopus 로고    scopus 로고
    • Reconfigurable computing in digital signal processing: A survey
    • R. Tessier, "Reconfigurable computing in digital signal processing: A survey.," Journal of VLSI Signal Processing, vol. 28, 2001, pp. 7-27.
    • (2001) Journal of VLSI Signal Processing , vol.28 , pp. 7-27
    • Tessier, R.1
  • 8
    • 33747080413 scopus 로고    scopus 로고
    • Virtex-4 user guide
    • Xilinx Inc, UG070, version 2.2, April
    • Xilinx Inc. "Virtex-4 user guide," UG070, version 2.2, http://www.xilinx.com/bvdocs/userguides/ug070.pdf, April 2007.
    • (2007)
  • 9
    • 19344370988 scopus 로고    scopus 로고
    • PowerPC Processor Block Reference Guide
    • Xilinx Inc, UG018, version 2.1, July
    • Xilinx Inc., "PowerPC Processor Block Reference Guide" UG018, version 2.1, http://www.xilinx.com/bvdocs/userguides/ug018.pdf, July 2005.
    • (2005)
  • 12
    • 51449121405 scopus 로고    scopus 로고
    • Jan S. Lim, Two-Dimensional Signal and ImageProcessing, Prentice Hall, 1990, pp.476-479.
    • Jan S. Lim, Two-Dimensional Signal and ImageProcessing", Prentice Hall, 1990, pp.476-479.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.