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Volumn 40, Issue 5, 2008, Pages 375-386

Review of various dynamic modeling methods and development of an intuitive modeling method for dynamic systems

Author keywords

Bayesian network; Dynamic fault tree; Reliability graph with general gates

Indexed keywords


EID: 51249115468     PISSN: 17385733     EISSN: None     Source Type: Journal    
DOI: 10.5516/NET.2008.40.5.375     Document Type: Review
Times cited : (20)

References (24)
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  • 10
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    • A Discrete-time Bayesian Network Reliability Modeling and Analysis Framework
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  • 11
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    • A Contiuous-Time Bayesian Network Reliability Modeling, and Analysis Framework
    • H. Boudali and J.B. Dugan, "A Contiuous-Time Bayesian Network Reliability Modeling, and Analysis Framework," IEEE Transactions of Reliability, 55, 86 (2006).
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  • 12
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    • Radyban: A Tool for Reliability Analysis of Dynamic Fault Trees through Conversion into Dynamic Bayesian Networks
    • S. Montani, L. Portinale, A. Bobbio, D. Codetta-Raiteri, "Radyban: A Tool for Reliability Analysis of Dynamic Fault Trees through Conversion into Dynamic Bayesian Networks," Reliability Engineering & System Safety, 93, 922(2008).
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  • 14
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    • GreatSPN 1.7: Graphical Editor and Analyzer for Timed and Stochastic Petri Nets
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    • Chiola, G.1    Franceschinis, G.2    Gaeta, R.3    Ribaudo, M.4
  • 15
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    • The Conversion of Dynamic Fault Trees to Stochastic Petri Nets, as a Case of Graph Transformation
    • D. Codetta-Raiteri, "The Conversion of Dynamic Fault Trees to Stochastic Petri Nets, as a Case of Graph Transformation," Electronic Notes in Theoretical Computer Science, 127, 45 (2005).
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  • 17
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    • Modeling of System Reliability using Petri Nets with Aging Tokens
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  • 19
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    • A New Approach to Modeling the System Reliability: Dynamic Reliability Block Diagrams
    • Newport Beach, USA, Jan. 23-26
    • S. Distefano, L. Xing, "A New Approach to Modeling the System Reliability: Dynamic Reliability Block Diagrams," Proceedings of Annual Reliability and Maintainability Symposium, Newport Beach, USA, Jan. 23-26, 2006.
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    • Distefano, S.1    Xing, L.2
  • 21
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    • FPGA-based Monte Carlo Simulation for Fault Tree Analysis
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  • 22
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  • 23
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    • Kim, M.C.1    Seong, P.H.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.