Efficient class of redundant residue number system

2007 IEEE International Symposium on Intelligent Signal Processing, WISP

Volumn , Issue , 2007, Pages

  Timarchi, Somayeh ^a   Navi, Keivan ^a  

^a SHAHID BEHESHTI UNIVERSITY   (Iran)

Author keywords

Carry free computations; Parallel arithmetic; Redundant residue number system; Signed digit (SD) number system; Stored unibit transfer (SUT) representation

Indexed keywords

COMPUTER NETWORKS; DIGITAL DEVICES; SIGNAL PROCESSING; TECHNICAL PRESENTATIONS;

CARRY-FREE COMPUTATIONS; PARALLEL ARITHMETIC; REDUNDANT RESIDUE NUMBER SYSTEM; SIGNED-DIGIT (SD) NUMBER SYSTEM; STORED-UNIBIT TRANSFER (SUT) REPRESENTATION;

DIGITAL ARITHMETIC;

EID: 51149114358     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/WISP.2007.4447506     Document Type: Conference Paper

References (29)

1. Avizienis, A., "Signed-Digit Number epresentations for Fast Parallel Arithmetic," IRE Trans. Electronic Computers, Vol. 10, pp. 389-400, September 1961.
2. Benaissa M. et al., "Diminished-1 Multiplier for a Fast Convolver and Correlator Using the Fermat Number Transform," IEE Proc. G, vol. 135, pp. 187-193, 1988.
3. Efstathiou C. et al., "On the Design of Modulo 2n _ 1 Adders," Proc. Eighth IEEE Int'l Conf. Electronics, Circuits & Systems, pp. 517-520, 2001.
4. Ercegovac M. D., "Effective coding for fast redundant adders using the radix-2 digit set {0, 1, 2, 3}," in proc. 31 st Asilomar Conf. Signals Systems and Computers, Nov. 1997, pp. 1163-1167.
5. Gonzalez, A. F., and P. Mazumder, "Redundant Arithmetic, Algorithms and Implementations," Integration: the VLSI Journal, Vol. 30, pp. 13-53, November 2000.
6. Jaberipur, G., B. Parhami, and M. Ghodsi, "A Class of Stored-Transfer Representations for Redundant Number Systems," Proc. 35th Asilomar Conf. Signals Systems and Computers, November 2001, pp. 1304-1308.
7. Jaberipur, G., B. Parhami, and M. Ghodsi, "Weighted Two-Valued Digit-Set Encodings: Unifying Efficient Hardware Representation Schemes for Redundant Number Systems," IEEE Trans. Circuits and Systems I, Vol. 52, No. 7, pp. 1348, 1357, July 2005.
8. Jaberipur, G., B. Parhami, and M. Ghodsi, "An Efficient Universal Addition Scheme for all Hybrid-Redundant Representations with Weighted Bit-Set Encoding," J. VLSI Signal Processing, Vol. 42, No. 2, pp. 149-158, February 2006.
9. W. K. Jenkins and B. J. Leon, "The use of residue number systems in the design of finite impulse response digital filters," IEEE Trans. Circuits Syst., vol. CAS-24, no. 4, pp. 191-201, Apr. 1977.
10. Israel Koren, Computer Arithmetic Algorithms, 2nd edition. Natick, MA: A K Peters Ltd, 2002. ISBN: 1-56881-160-8.
11. Kuninobu S., Nishiyama T., Edamatu H., Taniguchi T. and Takagi N., "Design Of HighSpeed MOS Multiplier And Divider Using Redundant Binary Representation", in IEEE Proc. 8th Symp. Computer Arithmetic, pp. 80-86, 1987.
12. Lehmer D.H., Proc. Second Symp. Large-Scale Digital Calculating Machinery, pp. 141-146, 1951.
13. Leibowitz L. M., "A Simplified Binary Arithmetic for the Fermat Number Transform," IEEE Trans. Acoustics, Speech, Signal Processing, vol. 24, pp. 356-359, 1976.
14. Lindström A., Nordseth M., Bengtsson L., and Omondi A.; "Arithmetic Circuits Combining Residue and Signed-Digit Representations", Proceedings of the Eighth Asia-Pacific Computer Systems Architecture Conference (ACSAC'03), Aizu-Wakamatsu City, Japan, Sept. 2003. Published by Springer-Verlag in Lecture Notes in Computer Science (LNCS) Vol. 2823,
15. Nagpal H. K., Jullien G. A., and Miller W. C., "Processor architectures for two-dimensional convolvers using a single multiplexed computational element with finite field arithmetic," IEEE Trans. Comp., vol. C-32, no. 11, pp. 989-1000, Nov. 1983.
16. Parhami B., "Computer arithmetic: algorithms and hardware designs", Oxford, 2002.
17. Phatak, D. S. and I. Koren, "Constant-Time Addition and Simultaneous Format Conversion Based on Redundant Binary Representations," IEEE Trans. Computers, Vol. 50, No. 11, pp. 1267-1278, November 2001.
18. Phatak, D. S., and I. Koren, "Hybrid Signed-Digit Number Systems: A Unified Framework for Redundant Number Representations with Bounded Carry Propagation Chains," IEEE Trans. Computers, Vol. 43, No. 8, pp. 880-891, August 1994.
19. Shugang Wei and Kensuke Shimizu, "A novel residue arithmetic hardware algorithm using a signed-digit number representation", IEICE Trans. inf & syst., vol. E83-D, no. 12, pp. 2056-2064, Dec. 2000.
20. Shugang Wei and Kensuke Shimizu, "Fast residue arithmetic multipliers based on signed digit number system", in IEEE 8th Conf. Electronics, Circuits and Systems, vol. 1, pp. 263-266, 2001.
21. M. A. Soderstrand, "A high-speed low-cost recursive digital filter using residue number arithmetic," Proc. IEEE, vol. 65, pp. 1065-1067, Jul. 1977.
22. Sunder S. at al., "Area-Efficient Diminished-I Multiplier for Fermat Number-Theoretic Transform," IEE Proc. G, vol. 140, pp. 211-215, 1993.
23. Takagi N., "High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree", IEEE Transactions on Computers, vol. c-34, no. 9, pp. 789-796, Sep. 1985.
24. Taylor F., "A Single Modulus ALU for Signal Processing", IEEE Trans. on Acoustics, Speech, Signal Processing, vol. 33, pp. 1302-1315, 1985.
25. Tyagi A., "A Reduced-Area Scheme for Carry-Select Adders," IEEE Trans. Computers, vol. 42, no. 10, pp. 1163-1170, Oct. 1993.
26. Vandemeulebroecke A., Vanzieleghem E., Denayer T. and Jespers P. G. A., "A New Carry-Free Division Algorithm and its Application to a Singler-Chip 1024-b RSA Processor", IEEE Journal of solid-state circuits, vol. 25, no. 3, pp. 748-756, Jun. 1990.
27. Shugang Wei and Kensuke Shimizu, "A novel residue arithmetic hardware algorithm using a signed-digit number representation", IEICE Trans. inf & syst., vol. E83-D, no. 12, pp. 2056-2064, Dec. 2000.
28. Wei Sh., and Shimizu K., "Fast residue arithmetic multipliers based on signed digit number system", in IEEE 8th Conf Electronics, Circuits and Systems, vol. 1, pp. 263-266, 2001.
29. Zimmermann R. et al., "A 177 Mb/s VLSI Implementation of the International Data Encryption Algorithm," IEEE J. Solid-State Circuits, vol. 29, no. 3, pp. 303-307, 1994.