FlexWAFE - A high-end real-time stream processing library for FPGAs

Proceedings - Design Automation Conference

Volumn , Issue , 2007, Pages 916-921

  Do Carmo Lucas, Amilcar ^a   Heithecker, Sven ^a   Ernst, Rolf ^a  

^a TECHNICAL UNIVERSITY OF BRAUNSCHWEIG   (Germany)

Author keywords

Communication centric; Digital film; FPGA; Reconfigurable; Stream based architecture; VLIW; Weakly programmable

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CONTROL EQUIPMENT; DIGITAL SIGNAL PROCESSING; FILM PREPARATION; IMAGE ANALYSIS; OPTICAL RESOLVING POWER; REAL TIME SYSTEMS;

COMMUNICATION CENTRIC; DIGITAL FILM; STREAM BASED ARCHITECTURE; STREAM PROCESSING LIBRARY; VHDL GENERICS; WEAKLY PROGRAMMABLE SYSTEMS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 34547240858     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2007.375295     Document Type: Conference Paper

References (24)

1. IEC 60027-2: Letter symbols to be used in electrical technology - Part 2: Telecommunications and electronics. IEC, 3.0 edition, August 2005.
2. Analog Devices Inc. Homepage.
3. C. M. Brislawn. Classification of nonexpansive symmetric extension transforms for multirate filter banks. In Applied and Computational Harmonic Analisys, volume 3, pages 337-357, 1996.
4. Discreet. Homepage.
5. A. do Carmo Lucas and R. Ernst. An Image Processor for Digital Film. In IEEE ASAP, July 2005.
6. A. do Carmo Lucas, S. Heithecker, P. Rtlffer, R. Ernst, H. Rückert, G. Wischermann, K. Gebel, R. Fach, W. Hunther, S. Eichner, and G. Scheller. A reconfigurable HW/SW platform for computation intensive high-resolution real-time digital film applications. In IEEE DATE, pages 194-199, March 2006.
7. S. Dutta, R. Jensen, and A. Rieckmann. Viper: A multiprocessor SoC for advanced set-top box and digital TV systems. In IEEE Design and Test of Computers, Sip, pages 21-31, Oct 2001.
8. S. Eichner, G. Scheller, U. Wessely, H. Rückert, and R. Hedtke. Motion compensated spatial-temporal reduction of film grain noise in the wavelet domain. In SMPTE Technical Conference, New York, 2005.
9. R. Hartenstein, A. Hirschbiel, and M. Weber. MOM - Map Oriented Machine. In Proceedings of the International Workshop on Hardware Accelerators, 1987.
10. S. Heithecker, A. do Carmo Lucas, and R. Ernst. A Mixed QoS SDRAM Controller for FPGA-Based High-End Image Processing. In Workshop on Signal Processing Systems Design and Implementation, page TP.11. IEEE, 2003.
11. S. Heithecker, A. do Carmo Lucas, and R. Ernst. A high-end real-time digital film processing reconfigurable platform. volume 2007, pages Article ID 85318,15 pages, 2007. doi:10.1155/2007/85318.
12. S. Heithecker and R. Ernst. Traffic Shaping for an FPGA-Based SDRAM Controller with Complex QoS Requirements. In Design Automation Conference (DAC), pages 575 - 578. ACM, June 2005.
13. Hunt Engineering Ltd. Homepage.
14. J. A. Kahle, M. N. Day, H. P. Hofstee, C. R. Johns, T. R. Maeurer, and D. Shippy. Introduction to the Cell multiprocessor. IBM Journal of Research and Development, 49(4/5):589-604, July/September 2005.
15. R. Karp and R. Miller. Properties of a model for Parallel Computations: Dterminancy, Termination Queueing. SIAM Journal of Applied Math, 40(6), November 1966.
16. E. A. Lee and D. G. Messerschmitt. Synchronous Data Flow. In Proceedings of the IEEE, volume 75, pages 1235 - 1245, September 1987.
17. Nallatech Inc. Homepage.
18. Oxford Micro Devices Inc. Homepage.
19. Quantel Ltd. Homepage.
20. S. Rout. Orthogonal vs. Biorthogonal Wavelets for Image Compression. Master's thesis, Virginia Polytechnic Institute and State University, 2003.
21. SGI Inc. Homepage.
22. R. Strzodka and C. Garbe. Real-Time Motion Estimation and Visualization on Graphics Cards. In Proceedings IEEE Visualization 2004, pages 545-552, 2004.
23. Texas Instruments Inc. Homepage.
24. Xilinx Inc. Homepage.