Production worthy 3D interconnect technology

2008 IEEE International Interconnect Technology Conference, IITC

Volumn , Issue , 2008, Pages 37-39

  Tu, H J ^a   Wu, W J ^a   Hu, J C ^a   Yang, K F ^a   Chang, H B ^a   Chiou, W C ^a   Yu, C H ^a  

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ARGON; CMOS INTEGRATED CIRCUITS; COMPUTER NETWORKS; COPPER; COST EFFECTIVENESS; INTEGRATED CIRCUITS; INTERCONNECTION NETWORKS; PHOTORESISTS; PRESSURE DROP; SILICON; SILICON WAFERS; THREE DIMENSIONAL; TUNGSTEN; WAFER BONDING;

INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE; METAL DIFFUSION; THROUGH-SILICON VIAS;

ASPECT RATIO;

EID: 50949123375     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2008.4546918     Document Type: Conference Paper

References (5)

1. K. N. Chen, S. H. Lee, Paul S. Andry, C. K. Tsang, A. W. Topol, Y. M. Lin, J. Q. Lu, A. M. Young, M. Ieong and W. Haensch, "Structure, Design and Process Control for Cu Bonded Interconnects in 3D Integrated Circuits," IEDM 2006.
2. B. Swinnen, W. Ruythooren, P. D. Moor, L. Bogaerts, L. Carbonell, K. D. Munck, B. Eyckens, S. Stoukatch, D. S. Tezcan, Z. Tokei, J. Vaes, J. V. Aelst and E. Beyne, "3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10 um pitch through-Si vias," IEDM, 2006.
3. P. R. Morrow, C. M. Park, S. Ramanathan, M. J. Korbinsky and M. Harmes, "Three-Dimensional Wafer Stacking Via Cu-Cu Bonding Integrated With 65-nm Strained-Su/Low-k CMOS Technology," IEEE ED Letters, Vol. 27, no.5, 2006, pp. 335-337.
4. D. Temple, C.A. Bower, D. Malta, J. E. Robinson, P. R. Coffman, M. R. Skokan and T. B. Welch, "High Density 3-D Integration Technology for Massively Parallel Signal Processing in Advanced Infrared Focal Plane Array Sensors," IEDM, 2006.
5. A. Jourdain, S. Stoukatch, P. De Moor, W. Ruythooren, S. Pargfrieder, B. Swinnen, and E. Beyne, "Simultaneous Cu-Cu and Compliant Dielectric Bonding for 3D Stacking of ICs", Proceedings of IITC 2007, p.207