FPGA implementation of a scalable shared buffer ATM switch

1998 1st IEEE International Conference on ATM, ICATM 1998

Volumn 1998-January, Issue , 1998, Pages 247-251

  Shim, Jae Wook ^a   Jeong, Gab Joong ^a   Lee, Moon Key ^a   Ahn, Seung Han ^b  

^a Yonsei University   (South Korea)

^b Hynix Semiconductor Inc   (South Korea)

Author keywords

FPGA; Scalability; Shared buffer

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); SCALABILITY;

ARRAY SIZES; ATM SWITCH; BUFFER CAPACITY; FPGA IMPLEMENTATIONS; MEMORY BLOCKS; OPERATING FREQUENCY; SHARED BUFFER; SHARED BUFFER ATM SWITCHES;

INTERNET PROTOCOLS;

EID: 85027144790     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICATM.1998.688184     Document Type: Conference Paper

References (5)

1. "B-IDSN ATM functional characteristics", Geneba, May 1990, CCITT SG XV III Draft Recommendation 1.150.
2. T. Kozaki et.al, "32×32 Shared Buffer Type ATM Switch VlSI's for B-ISDN's", IEEE J. Select. Areas Commun., vol. 9, no. 8, Oct. 1991, pp. 1239-1247.
3. N. Endo et al.", Shared Buffer Memory Switch for an ATM Exchange", IEEE Trans. Commun., vol. 41, no. 1, Jan. 1993, pp. 237-245
4. G. J. Jeong, K. H. Kwon, M. K. Lee, and S. H. Ahn, "High throughput systolic memory architecture using three directional data flows", Proc. IEEE ICECS, Rodos, Greece, Oct. 1996, pp. 667-670.
5. K. H. Kwon, G. J. Jeong, M. K. Lee, and S. H. Ahn, "A scalable memory system design", Proc. Int. Conf. VLSI Design, Hyderabad, India, Jan. 1997, pp. 257-260.