On the design and implementation of a RISC processor extension for the KASUMI encryption algorithm

Computers and Electrical Engineering

Volumn 34, Issue 6, 2008, Pages 531-546

  Balderas Contreras, Tomas ^a   Cumplido, Rene ^a   Feregrino Uribe, Claudia ^a  

^a INSTITUTO NACIONAL DE ASTROFÍSICA   (Mexico)

Author keywords

Block cipher; Cryptography; Hardware implementation; KASUMI; RISC Processors

Indexed keywords

ALGORITHMS; CELLULAR NEURAL NETWORKS; CELLULAR TELEPHONE SYSTEMS; CRYPTOGRAPHY; MOBILE TELECOMMUNICATION SYSTEMS; RADIO BROADCASTING; RADIO TRANSMISSION; REDUCED INSTRUCTION SET COMPUTING; RELIABILITY; TELEPHONE SYSTEMS;

BLOCK CIPHER; CELLULAR NETWORKS; CORE NETWORKS; DATA CONFIDENTIALITY; DATA-INTEGRITY; DESIGN TECHNIQUES; ENCRYPTION ALGORITHM; HARDWARE IMPLEMENTATION; HIGH DATA RATES; IP-BASED NETWORKS; KASUMI; KASUMI BLOCK CIPHER; LOW-POWER CONSUMPTION; ORDERS-OF-MAGNITUDE; PERFORMANCE IMPROVEMENTS; PROCESSOR CORES; PROPOSED ARCHITECTURES; RADIO INTERFACES; RISC PROCESSOR; RISC PROCESSORS; UNIVERSAL MOBILE TELECOMMUNICATIONS SYSTEM;

INTERNET PROTOCOLS;

EID: 50849101397     PISSN: 00457906     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.compeleceng.2007.11.003     Document Type: Article

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