A 1.6-880MHz synthesizable ADPLL in 0.13um CMOS

2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT

Volumn , Issue , 2008, Pages 9-12

  Chang, Hsiang Hui ^a   Lee, Shang Ming ^a   Chou, Chao Wen ^a   Chang, Yu Tung ^a   Cheng, Yi Li ^a  

^a MEDIATEK INC   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER NETWORKS; INDUSTRIAL ENGINEERING;

CMOS TECHNOLOGIES; INTERNATIONAL SYMPOSIUM; VLSI DESIGNS;

PHASE LOCKED LOOPS;

EID: 50649115978     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VDAT.2008.4542400     Document Type: Conference Paper

References (5)

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2. T. Watanabe, et aI., "An All-Digital PLL for Frequency Multiplication by 4 to 1022 With Seven-Cycle Lock Time," IEEE J Solid-State Circuits, vol. 2, pp. 198-204, Feb. 2003.
3. L. Xiu, et aI., "A Novel All-Digital PLL With Software Adaptive Filter," IEEE J Solid-State Circuits, vol. 39, pp. 476-483, Mar. 2004.
4. T. Olsson, et al., "A Digitally Controlled PLL for SoC Applications," IEEE J Solid-State Circuits, vol. 39, pp. 751-760, May. 2004.
5. R. B. Staszewski, et al., "A Digitally Controlled Oscillator in a 90nm Digital CMOS Process for Mobile Phones," IEEE J. Solid-State Circuits, vol. 40, pp. 2203-2211, Nov. 2005.