Energy and performance evaluation of an FPGA-based SoC platform with AES and PRESENT coprocessors

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 5114 LNCS, Issue , 2008, Pages 106-115

  Guo, Xu ^a   Chen, Zhimin ^a   Schaumont, Patrick ^a  

^a VIRGINIA POLYTECHNIC INSTITUTE AND STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER NETWORKS; COMPUTER SYSTEMS; EFFICIENCY; ENERGY EFFICIENCY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; INTEGRATED CIRCUITS; PROGRAMMABLE LOGIC CONTROLLERS;

BLOCK CIPHERS;

EMBEDDED SYSTEMS;

EID: 50649083065     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-70550-5_12     Document Type: Conference Paper

References (10)

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2. McLoone, M., McCanny, J.: High Performance Single Chip FPGA Rijndael Algorithm Implementations. In: Koç, Ç.K., Naccache, D., Paar, C. (eds.) CHES 2001. LNCS, vol. 2162, pp. 65-76. Springer, Heidelberg (2001)
3. Good, T., Benaissa, M.: AES from the fastest to the smallest. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659. pp. 427-440. Springer, Heidelberg (2005)
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5. The GEZEL homepage, http://rijndael.ece.vt.edu/gezel2
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8. Eisenbarth, T., Kumar, S., Paar, C., Poschmann, A., Uhsadel, L.: A Survey of Lightweight Cryptography Implementations. IEEE Design and Test of Computers - Special Issue on Secure ICs for Secure Embedded Computing 24, 522-533 (2007)
9. Bogdanov, A., et al.: PRESENT: An Ultra-Lightweight Block Cipher. In: Paillier, P., Verbauwhede, I. (eds.) CHES 2007. LNCS, vol. 4727, pp. 450-466. Springer, Heidelberg (2007)
10. Schaumont, P., Ching, D., Verbauwhede, I.: An Interactive Codesign Environment for Domain-specific Coprocessors. ACM Transactions on Design Automation of Electronic Systems 11(1), 70-87 (2006)