Improving solder joint reliability of WLP by means of a compliant layer

Proceedings of the IEEE/CPMT International Electronics Manufacturing Technology (IEMT) Symposium

Volumn , Issue , 2006, Pages 93-101

  Lee, Hun Kwang ^a   Lee, Sai Mun ^a   Soo, Yik Foong ^a   Wong, Seck Jiong ^a  

^a Bayan Lepas Free Industrial Zone   (Malaysia)

Author keywords

[No Author keywords available]

Indexed keywords

BRAZING; FINITE ELEMENT METHOD; NONMETALS; SILICON; SILICON WAFERS; TECHNOLOGY; WELDING;

COMPLIANT LAYER; CYCLIC LOADINGS; ELECTRONICS MANUFACTURING; FATIGUE-LIFE; FINITE ELEMENT MODELING; IN-BETWEEN; INTERNATIONAL CONFERENCES; LOW-MODULUS; METALLIZATION; SILICON CHIPS; SOLDER JOINT RELIABILITY; SOLDER JOINTS; WAFER-LEVEL PACKAGE;

SOLDERING ALLOYS;

EID: 50249174425     PISSN: 10898190     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEMT.2006.4456439     Document Type: Conference Paper

References (3)

1. A. Yeo, C. Lee, J. H. L. Pang, "Flip Chip Solder Joint Fatigue Analysis Using 2D and 3D Models," Proceedings of 5th International Conference on Thermal and Mechanical Simulation and Experiments in Micro-electronics and Micro-Systems, 2004, pp. 549-555.
2. J. Lau, W. Dauksher, P. Vianco, "Acceleration Models, Constitutive Equations, and Reliability of Lead-Free Solder and Joints," Proceedings of Electronic Components and Technology Conference, 2003, pp. 229-236.
3. J. Lau, D. Shangguan, D. C. Y. Lau, T. T. W. Kung, S. W. R. Lee, "Thermal-Fatigue Life Prediction Equation for Wafer-Level Chip Scale Package (WLCSP) Lead-Free Solder Joints on Lead-Free Printed Circuit Board (PCB)," Proceedings of Electronic Components and Technology Conference, 2004, pp. 1563-1569.