Advantages of a new scheme of junction profile engineering with laser spike annealing and its integration into a 45-nm node high performance CMOS technology

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2007, Pages 122-123

  Yamamoto, T ^a   Kubo, T ^a   Sukegawa, T ^a   Katakami, A ^a   Shimamune, Y ^a   Tamura, N ^a   Ohta, H ^a   Miyashita, T ^a   Sato, S ^a   Kase, M ^a   Sugii, T ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DRAIN CURRENT; SILICON ON INSULATOR TECHNOLOGY; VLSI CIRCUITS;

CONVENTIONAL TECHNIQUES; DEVICE PERFORMANCE; ENGINEERING TECHNIQUES; HIGH-PERFORMANCE CMOS TECHNOLOGY; JUNCTION PROFILES; LOW SENSITIVITY; PARASITIC RESISTANCES; ULTRAHIGH TEMPERATURE;

CMOS INTEGRATED CIRCUITS;

EID: 47249157625     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2007.4339752     Document Type: Conference Paper

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