Junction profile engineering with a novel multiple laser spike annealing scheme for 45-nm node high performance and low leakage CMOS technology

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2007, Pages 143-146

  Yamamoto, T ^a   Kubo, T ^a   Sukegawa, T ^a   Takii, E ^a   Shimamune, Y ^a   Tamura, N ^a   Sakoda, T ^a   Nakamura, M ^a   Ohta, H ^a   Miyashita, T ^a   Kurata, H ^a   Satoh, S ^a   Kase, M ^a   Sugii, T ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DRAIN CURRENT; ELECTRON DEVICES;

CMOS TECHNOLOGY; JUNCTION LEAKAGE CURRENTS; JUNCTION PROFILES; MULTIPLE LASERS; PARASITIC RESISTANCES; SOURCE-DRAIN; SOURCE-DRAIN EXTENSIONS; SPIKE ANNEALING;

CMOS INTEGRATED CIRCUITS;

EID: 50249136642     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2007.4418885     Document Type: Conference Paper

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