New etch challenges for the 65-nm technology node Low-k integration using An enhanced Trench First Hard Mask architecture

2006 International Interconnect Technology Conference, IITC

Volumn , Issue , 2006, Pages 36-38

  Posseme N ^a   Maurice, C ^b   Brun, Ph ^a   Ollier, E ^c   Guillermet, M ^a   Verove C ^d   Berger, T ^d   Fox, R ^b   Hinsinger, O ^d  

^a CEA LETI   (France)

^b FREESCALE SEMICONDUCTOR INC   (United States)

^c NXP SEMICONDUCTORS   (Netherlands)

^d STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; NANOTECHNOLOGY;

65NM TECHNOLOGY; ELECTRICAL DATA; HARD MASKS; INTEGRATION SCHEMES; INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE; LOW-K INTEGRATION; TECHNOLOGY NODES; YIELD IMPROVEMENTS;

TECHNOLOGY;

EID: 50249105310     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2006.1648639     Document Type: Conference Paper

References (7)

1. D.L. Keil et al, "Review of Trench and via plasma issues tor copper dual damascene in undoped and fluorine-doped silicate glass oxide", J. Vac. Sci. Technol. B21 (5). Sep/Oct 2003
2. O. Hinsinger et al., "Demonstration of an extendable and industrial 300mm BEOL integration for the 65-nm technology node," IEDM Technical Digest, pp. 317-320, 2004.
3. R.Fox et al., "High Performance k=2.5 ULK Backend Solution Using an Improved TFHM Architecture, Extendible to the 45nm Technology Node", IEDM Technical Digest, 2005.
4. D. Shamiryan et al, J.Vac. Sci. Technol. B. 20, 1923, 2002.
5. O. Louveau et al, Microelectronic Engineering, 73, 351, 2004.
6. Y. Furukawa et al, Microelectronic Engineering, 76, 25, 2004.
7. E.A. Hudson et al, "Minimizing low-k damage during in-situ Photoresist strip", p62, AVS (Nov 14-19), 2004.