-
1
-
-
50249153671
-
-
International Technology Roadmap for Semiconductors, ITRS
-
International Technology Roadmap for Semiconductors, ITRS, 2006. http://public.itrs.net/
-
(2006)
-
-
-
2
-
-
0141837018
-
Trends and challenges in VLSI circuit reliability
-
Jul.-Aug
-
C. Constantinescu, "Trends and challenges in VLSI circuit reliability," IEEE Micro, vol.23, Jul.-Aug. 2003, pp. 14-19.
-
(2003)
IEEE Micro
, vol.23
, pp. 14-19
-
-
Constantinescu, C.1
-
3
-
-
0033712183
-
BDS: A BDD-based logic optimization system
-
June
-
C. Yang, M. Ciesielski, and V. Singhal, "BDS: a BDD-based logic optimization system," in Proc. ACM/IEEE Design Automation Conf., June 2000, pp. 92-97.
-
(2000)
Proc. ACM/IEEE Design Automation Conf
, pp. 92-97
-
-
Yang, C.1
Ciesielski, M.2
Singhal, V.3
-
4
-
-
34047106816
-
Analysis and Synthesis of Quantum Circuits by Using Quantum Decision Diagrams
-
Mar
-
Afshin Abdollahi and Massoud Pedram, "Analysis and Synthesis of Quantum Circuits by Using Quantum Decision Diagrams," Proc. of Design Automation and Test in Europe, Mar. 2006, pp. 317-322.
-
(2006)
Proc. of Design Automation and Test in Europe
, pp. 317-322
-
-
Abdollahi, A.1
Pedram, M.2
-
5
-
-
0003133883
-
Probabilistic logics and the synthesis of reliable organisms from unreliable components
-
C. E. Shannon and J. McCarthy, eds, pp, Princeton Univ. Press, Princeton, N.J
-
J. von Neumann, "Probabilistic logics and the synthesis of reliable organisms from unreliable components," in Automata Studies (C. E. Shannon and J. McCarthy, eds.), pp. 43-98, Princeton Univ. Press, Princeton, N.J., 1954.
-
(1954)
Automata Studies
, pp. 43-98
-
-
von Neumann, J.1
-
6
-
-
0023979062
-
Reliable Computation by Formulas in the Presence of Noise
-
N. Pippenger, "Reliable Computation by Formulas in the Presence of Noise", IEEE Trans on Inf. Theory, vol. 34(2), pp. 194-197, 1988.
-
(1988)
IEEE Trans on Inf. Theory
, vol.34
, Issue.2
, pp. 194-197
-
-
Pippenger, N.1
-
7
-
-
24344473023
-
Bifurcations and Fundamental Error Bounds for Fault-Tolerant Computations
-
July
-
J. B. Gao, Yan Qi and J.A.B. Fortes,"Bifurcations and Fundamental Error Bounds for Fault-Tolerant Computations" IEEE Transactions on Nanotechnology, vol. 4-4 pp. 395-402, July 2005.
-
(2005)
IEEE Transactions on Nanotechnology
, vol.4 -4
, pp. 395-402
-
-
Gao, J.B.1
Qi, Y.2
Fortes, J.A.B.3
-
8
-
-
33646950897
-
Probability Analysis of Combination Systems and their Reliability
-
Nov-Dec
-
V. L. Levin,"Probability Analysis of Combination Systems and their Reliability,"Engin. Cybernetics, no 6. Nov-Dec. 1964, pp. 78-84.
-
(1964)
Engin. Cybernetics
, Issue.6
, pp. 78-84
-
-
Levin, V.L.1
-
9
-
-
33744479056
-
Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models
-
May
-
K.N. Patel, J.P. Hayes, and I.L. Markov, "Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models," IWLS, May 2003, pp. 59-64.
-
(2003)
IWLS
, pp. 59-64
-
-
Patel, K.N.1
Hayes, J.P.2
Markov, I.L.3
-
10
-
-
33646902164
-
-
S. Krishnaswamy, G. F. Viamontes, I. L. Markov, J. P. Hayes, Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices, In Proc. of the Design, Automation and Test Europe Conference, March 2005, pp. 282-287.
-
S. Krishnaswamy, G. F. Viamontes, I. L. Markov, J. P. Hayes, "Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices," In Proc. of the Design, Automation and Test Europe Conference, March 2005, pp. 282-287.
-
-
-
-
12
-
-
0346148456
-
A Probabilistic Based Design Methodology for Nanoscale Computation
-
R.I. Bahar, J. Mundy and J. Chan, "A Probabilistic Based Design Methodology for Nanoscale Computation", ICCAD, 2003, pp. 480486.
-
(2003)
ICCAD
, pp. 480486
-
-
Bahar, R.I.1
Mundy, J.2
Chan, J.3
-
13
-
-
84903828974
-
Representation of Switching Circuits by Binary Decision Programs
-
C. Y. Lee, "Representation of Switching Circuits by Binary Decision Programs," Bell System Technical Journal, vol. 38, no. 4, 1959, pp. 985-999.
-
(1959)
Bell System Technical Journal
, vol.38
, Issue.4
, pp. 985-999
-
-
Lee, C.Y.1
-
15
-
-
0022769976
-
Graph-Based Algorithms for Boolean Function Manipulation
-
R. Bryant, "Graph-Based Algorithms for Boolean Function Manipulation," IEEE Transactions on Computers, vol. 35, 1986, pp. 677-691.
-
(1986)
IEEE Transactions on Computers
, vol.35
, pp. 677-691
-
-
Bryant, R.1
-
16
-
-
77149158234
-
Efficient Implementation of a BDD Package
-
K. Brace, R. Rudell, and R. Bryant, "Efficient Implementation of a BDD Package," Design Automation Conference, 1990, pp. 4045.
-
(1990)
Design Automation Conference
, pp. 4045
-
-
Brace, K.1
Rudell, R.2
Bryant, R.3
-
17
-
-
0028483037
-
EVBDD-Based Algorithms for Integer Linear Programming, Spectral Transformation, and Function Decomposition
-
Y.-T. Lai, M. Pedram, and S. Vrudhula, "EVBDD-Based Algorithms for Integer Linear Programming, Spectral Transformation, and Function Decomposition," IEEE Transactions on Computer-Aided Design, vol. 8, 1994, pp. 959-975.
-
(1994)
IEEE Transactions on Computer-Aided Design
, vol.8
, pp. 959-975
-
-
Lai, Y.-T.1
Pedram, M.2
Vrudhula, S.3
-
18
-
-
85150403978
-
-
M. Jaeger, Probabilistic decision graphs-combining verification and AI techniques for probabilistic inference, International Journal of Uncertainty, Fuzziness and Knowledge-Based Systems archive, 12, Issue SUPPLEMENT, 2004, pp. 1942.
-
M. Jaeger, "Probabilistic decision graphs-combining verification and AI techniques for probabilistic inference," International Journal of Uncertainty, Fuzziness and Knowledge-Based Systems archive, Volume 12, Issue SUPPLEMENT, 2004, pp. 1942.
-
-
-
-
19
-
-
0029209733
-
Probabilistic manipulation of boolean functions using free boolean diagrams
-
A. Shen, S.Devadas and A. Ghosh, "Probabilistic manipulation of boolean functions using free boolean diagrams," IEEE transactions on computer-aided design of integrated circuits and systems, 1995, vol. 14, no1, pp. 87-95.
-
(1995)
IEEE transactions on computer-aided design of integrated circuits and systems
, vol.14
, Issue.NO1
, pp. 87-95
-
-
Shen, A.1
Devadas, S.2
Ghosh, A.3
-
21
-
-
0031120689
-
The K*BMD: A Verification Data Structure
-
R. Drechsler, B. Becker and S. Ruppertz, "The K*BMD: A Verification Data Structure," IEEE Design and Test of Computers 14(2), 1997, pp. 51-59.
-
(1997)
IEEE Design and Test of Computers
, vol.14
, Issue.2
, pp. 51-59
-
-
Drechsler, R.1
Becker, B.2
Ruppertz, S.3
|