Control of process-induced damages in self-assembled porous silica /Cu damascene interconnects for 45nm node and beyond

Digest of Technical Papers - Symposium on VLSI Technology

Volumn 2005, Issue , 2005, Pages 146-147

  Yagi, R ^a   Chikaki, S ^a   Shimoyama, M ^a   Yoshino, T ^b   Ono, T ^a   Ishikawa, A ^a   Fujii, N ^a   Hata, N ^b   Nakayama, T ^a   Kohmura, K ^a   Tanaka, H ^a   Goto, T ^a   Kawahara, J ^a   Sonoda, Y ^a   Matsuo, H ^a   Seino, Y ^b   Kinoshita, K ^a   Kikkawa, T ^a,c  

^a ASSOCIATION OF SUPER ADVANCED ELECTRONICS TECHNOLOGIES ASET   (Japan)

^b NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY AIST   (Japan)

^c HIROSHIMA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; COPPER; PERMITTIVITY; POROUS MATERIALS; SILICA; VAPORS;

1,3,5,7-TETRAMETHYLCYCLOTETRASILOXANE; DAMASCENE; PROCESS-INDUCED DAMAGES; SILICA /CU DAMASCENE INTERCONNECTS;

SELF ASSEMBLY;

EID: 28744453409     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/.2005.1469247     Document Type: Conference Paper

References (6)

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3. T. Ono, et al., Proc. Dry Process Symp., p. 229 (2004)
4. T. Jacobs, et al., Proc. 2002 IITC., p. 236 (2002)
5. E. R. Guyer, et al., Proc. 2004 IITC., p. 236 (2004)
6. K. Kohmura et al., Mat. Res. Soc. Symp. Proc. Vol.812, F6. 2 (2004)