Parallelized radix-2 scalable Montgomery multiplier

2007 IFIP International Conference on Very Large Scale Integration, VLSI-SoC

Volumn , Issue , 2007, Pages 146-150

  Jiang, Nan ^a   Harris, David ^a  

^a HARVEY MUDD COLLEGE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FREQUENCY MULTIPLYING CIRCUITS; LSI CIRCUITS; PROGRAMMABLE LOGIC CONTROLLERS;

FPGA IMPLEMENTATIONS; INTERNATIONAL CONFERENCES; LOOK-UP-TABLES; MODULAR EXPONENTIATION; MONTGOMERY; RADIX-2; SCALABLE RADIX-2; SPEED IMPROVEMENT; VERY LARGE-SCALE INTEGRATION;

MULTIPLYING CIRCUITS;

EID: 50149114755     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSISOC.2007.4402488     Document Type: Conference Paper

References (8)

1. P. Montgomery, "Modular multiplication without trial division," Math. Of Computation, vol. 44, no. 170, pp. 519-521, April 1985.
2. A. Tenca and Ç. Koç, "A scalable architecture for modular multiplication based on Montgomery's algorithm," IEEE Trans. Computers, vol. 52, no.9, pp. 1215-1221, Sept. 2003.
3. D. Harris et al., "An improved unified scalable radix-2 Montgomery multiplier", IEEE Symp. Computer Arithmetic, pp. 172-178, 2005.
4. N. Jiang and O. Harris, "Quotient piplelined very high radix scalable Montgomery multipliers", Proc. Asilomar Conf. Signal, Systems , and Computers 2006
5. K. Kelly and D. Harris, "Parallelized very high radix scalable Montgomery multipliers," Proc. Asilomar Conf. Signals, Systems, and Computers, pp. 1196-1200, 2005.
6. K. Kelley and D. Harris, "Very high radix scalable Montgomery multipliers", IEEE IWSOC Conference, pp. 400-404, July 2005.
7. th IEEE Symp. Computer Arithmetic, pp. 193-199, 1995.
8. Xiiinx, Virtex-II Pro and Virtex-II Pro X Platform FPGAs Datasheet, June 30, 2004, www.xiiinx.com