Parallelized very high radix scalable montgomery multipliers

Conference Record - Asilomar Conference on Signals, Systems and Computers

Volumn 2005, Issue , 2005, Pages 1196-1200

  Kelley, Kyle ^a   Harris, David ^a  

^a HARVEY MUDD COLLEGE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT MODULAR EXPONENTIATION; MONTGOMERY MULTIPLIERS; MULTIPLICATIONS;

BANDWIDTH; COMPUTATIONAL METHODS; REDUNDANCY; TABLE LOOKUP;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 33847653361     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)

1. T. Blum and C. Paar, "High-radix Montgomery multiplication on reconfigurable hardware," IEEE Trans. Computers, vol. 50, no. 7, pp. 759-764, July 2001.
2. S. Eldridge and C. Walter, "Hardware implementation of Montgomery's modular multiplication algorithm," IEEE Trans. Computers, vol. 42, no. 6, pp. 693-699, June 1993.
3. G. Gaubatz, "Versatile Montgomery multiplier architectures," M.S. Thesis, Worcester Polytechnic Institute, Dept of Electrical Engineering, April 2002.
4. D. Harris et al., "An improved unified scalable radix-2 Montgomery multiplier", to appear in IEEE Symp. Computer Arithmetic, 2005.
5. K. Kelley and D. Harris, "Very high radix scalable Montgomery multipliers", to appear in IEEE IWSOC Conference, July 2005.
6. P. Kornerup, "High-radix modular multiplication for cryptosystems," Proc 11th IEEE Symp. Computer Arithmetic, pp. 277-283, 1993.
7. P. Kornerup, "A systolic, linear-array multiplier for a class of right-shift algorithms," IEEE Trans. Computers, vol. 43, no. 8, pp. 892-898, August 1994.
8. P. Montgomery, "Modular multiplication without trial division," Math. Of Computation, vol. 44, no. 170, pp. 519-521, April 1985.
9. K. Mukaida, M. Takenaka, N. Torii, and S. Masui, "Design of high-speed and area-efficient Montgomery modular multiplier for RSA algorithm," IEEE Symp. VLSI Circuits, pp. 320-323, 2004.
10. H. Orup and P. Kornerup, "A high-radix hardware algorithm for calculating the exponential ME Modulo N," Proc. 10th IEEE Symp. Computer Arithmetic, pp. 51-56, 1991.
11. H. Orup, "Simplifying quotient determination in high-radix modular multiplication," Proc. 12th IEEE Symp. Computer Arithmetic, pp. 193-199, 1995.
12. M. Shand and J. Vuillemin, "Fast implementations of RSA cryptography," Proc. 11th IEEE Symp. Computer Arithmetic, pp. 252-259, 1993.
13. A. Tenca and Ç. Koç, "A scalable architecture for modular multiplication based on Montgomery's algorithm," IEEE Trans. Computers, vol. 52, no.9, pp. 1215-1221, Sept. 2003.
14. A. Tenca and L. Tawalbeh, "An efficient and scalable radix-4 modular multiplier design using recoding techniques," Proc Asilomar Conf. Signals, Systems, and Computers, pp. 1445-1450, 2003.
15. G. Todorov, "ASIC design, implementation and analysis of a scalable high-radix Montgomery multiplier," M.S. Thesis, Oregon State University, June 2001.
16. Xilinx, Virtex-II Pro and Virtex-II Pro X Platform FPGAs Datasheet, June 30, 2004, www.xilinx.com