Efficient and high-throughput implementations of AES-GCM on FPGAs

ICFPT 2007 - International Conference on Field Programmable Technology

Volumn , Issue , 2007, Pages 185-192

  Zhou, Gang ^a   Michalik, Harald ^a   Hinsenkamp, László ^b  

^a TECHNICAL UNIVERSITY OF BRAUNSCHWEIG   (Germany)

^b DSI GmbH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

HIGH THROUGHPUTS; INTERNATIONAL CONFERENCES; MODULAR MULTIPLICATION; PAPER ADDRESSES;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); THROUGHPUT;

TECHNOLOGY;

EID: 50149106526     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2007.4439248     Document Type: Conference Paper

References (18)

1. D. A. McGrew and J. Viega, "The Galois/Counter Mode of Operation (GCM)," Updated submission to NIST, Modes of Operation Process, May 2005.
2. B. Yang, S. Mishra, and R. Karri, "High Speed Architecture for Galois/Counter Mode of Operation (GCM)," http://eprint.iacr.org/2005/ 146.pdf, 2005.
3. A. Satoh, "High-speed hardware architectures for authenticated encryption mode GCM," in Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on, May 2006.
4. Xilinx, "Virtex-4 User Guide, V1.5," Mar. 2006, http://www.xilinx.com.
5. _, "Virtex-5 User Guide, V2.1," Oct. 2006, http://www.xilinx. com.
6. m)," in Proceedings of the International Conference on Computer Science and Technology, 2003.
7. m), " IEEE Transaction on Computers, vol. 53, no. 8, pp. 945-959, Aug. 2004.
8. V. Rijmen, "Efficient Implementation of the Rijndael S-box," http://www.esat.kuleuven.ac.be/~rijmen/rijndael/sbox.pdf, 2000.
9. X. Zhang and K. K. Parhi, "High-Speed VLSI Architectures for the AES Algorithm," IEEE Transaction on VLSI, vol. 12, no. 9, pp. 957-967, 2004.
10. K. U. Jaervinen, M. T. Tommiska, and J. O. Skyttae, "A Fully Pipelined Memoryless 17.8Gbps AES-128 Encrypto," FPGA, 2003.
11. NIST, "Advanced Encryption Standard (AES)," FIPS Publication 197, Nov. 26, 2001.
12. F.-X. Standaert, G. Rouvroy, J.-J. Quisquater, and J.-D. Legat, "Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs," Cryptographic Hardware and Embedded Systems (CHES), 2003.
13. A. Hodjat and I. Verbauwhede, "A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA," in Proceedings ofthe 12th Annual IEEE Symposium on Field-Programming Custom Computing Machines, FCCM'04, 2004.
14. T. Good and M. Benaissa, "AES on FPGA: from the fastest to the smallest," Cryptographic Hardware and Embedded Systems (CHES), 2005.
15. J. Viega and D. A. McGrew, "The Use of Galois/Counter Mode (GCM) in IPsec Encapsulating Security Payload," RFC 4106, Network Working Group, June 2005.
16. Elliptic Semiconductor, "http://www.ellipticsemi.com."
17. Helion Technology, "http://www.heliontech.com."
18. Jetstream Media Technologies, "http://www.jetsmt.com."