Converting PLC instruction sequence into logic circuit: A preliminary study

IEEE International Symposium on Industrial Electronics

Volumn 4, Issue , 2006, Pages 2930-2935

  Ichikawa, Shuichi ^a   Akinaka, Masanori ^a   Ikeda, Ryo ^a   Yamamoto, Hiroshi ^a  

^a TOYOHASHI UNIVERSITY OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CONCURRENCY CONTROL; DESIGN; ELECTRIC NETWORK ANALYSIS; INDUSTRIAL ELECTRONICS; LOGIC CIRCUITS; LOGIC DESIGN; SWITCHING CIRCUITS; SWITCHING THEORY; TELEPHONE SYSTEMS;

CONTROL LOGICS; CONTROL PROGRAMS; DESIGN FRAMEWORK; INTERNATIONAL SYMPOSIUM; MITSUBISHI ELECTRIC; RECONFIGURABLE DEVICES; SEQUENTIAL DESIGNS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 50049092189     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISIE.2006.296082     Document Type: Conference Paper

References (14)

1. IEEE standard VHDL language reference manual, 2002, IEEE Std 1076-2002.
2. M. A. Adamski and J. L. Monteiro, "PLD implementation of logic controllers," in Proc. IEEE Int'l Symp. Industrial Electronics (ISIE'95), vol. 2, 1995, pp. 706-711.
3. M. Adamski and J. L. Monteiro, "From interpreted Petri net specification to reprogrammable logic controller design," in Proc. IEEE Int'l Symp. Industrial Electronics (ISIE 2000), vol. 1, 2000, pp. 13-19.
4. M. Wegrzyn, M. A. Adamski, and J. L. Monteiro, "The application of reconfigurable logic to controller design," Control Engineering Practice, vol. 6, pp. 879-887, 1998.
5. A. Wegrzyn and M. Wegrzyn, "Petri net-based specification, analysis and synthesis of logic controllers," in Proc. IEEE Int'l Symp. Industrial Electronics (ISIE 2000), vol. 1, 2000, pp. 20-26.
6. M. Ikeshita, Y. Takeda, H. Murakoshi, N. Funakubo, and I. Miyazawa, "An application of FPGA to high-speed programmable controller - development of the conversion program from SFC to Verilog-," in Proc. 7th IEEE Int'l Conf. Emerging Technologies and Factory Automation (ETFA'99), vol. 2, 1999, pp. 1386-1390.
7. I. Miyazawa, T. Nagao, M. Fukagawa, Y. Ito, T. Mizuya, and T. Sekiguchi, "Implementation of ladder diagram for programmable controller using FPGA," in Proc. 7th IEEE Int'l Conf. Emerging Technologies and Factory Automation (ETFA'99), vol. 2, 1999, pp. 1381-1385.
8. J. T. Welch and J. Carletta, "A direct mapping FPGA architecture for industrial process control applications," in Proc. Int'l Conf. Computer Design (ICCD2000), 2000, pp. 595-598.
9. Mitsubishi Electric Corp., Programming Manual II: The FX series of programmable controller (FX1S/FX1N/FX2N/FX1NC/FX2NC), April 2003, JY992D88101 rev. D.
10. _, "MELFANS web," 2004, http://wwwf2.mitsubishielectric.co.jp/ melfansweb/english/index.html.
11. M. Chiang and R. Palkovic, "LCC simulators speed development of synchronous hardware," Computer Design, vol. 25, no. 5, pp. 87-92, 1986.
12. E. Coffman, Ed., Computer and Job-shop Scheduling Theory. John Wiley & Sons, 1976.
13. M. J. Gonzalez, "Deterministic processor scheduling," ACM Computing Surveys, vol. 9, no. 3, pp. 173-204, 1977.
14. Altera Corp., APEX 20K Programmable Logic Device Family Data Sheet, March 2004, DS-APEX20K-5.1.