Design methodology of regular logic bricks for robust integrated circuits

IEEE International Conference on Computer Design, ICCD 2006

Volumn , Issue , 2006, Pages 162-167

  Kim, Yaw Tong ^a   Rovner, Vyacheslav ^a   Pileggi, Lawrence T ^a   Kheterpal, Veerbhan ^b  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b Fabbrix Inc

Author keywords

Circuit design; Manufacturability; Regularity; Synthesis

Indexed keywords

CIRCUIT DESIGN; COMPUTER DESIGNS; DESIGN METHODOLOGIES; DIRECT CONTROL; DIRECT MAPPING; IC DESIGNS; INTERNATIONAL CONFERENCES; MANUFACTURABILITY; NANOSCALE TECHNOLOGIES; ONE WAY; REGULARITY; SYNTHESIS; SYNTHESIS TOOLS;

BRICK; BRICKMAKING; ELECTRONICS INDUSTRY; INTEGRATED CIRCUITS; NANOTECHNOLOGY;

BUILDING MATERIALS;

EID: 49749150103     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2006.4380810     Document Type: Conference Paper

References (14)

1. T. Jhaveri, et al. "Maximization of layout printability/ manufacturability by extreme layout regularity," SPIE 2006.
2. A. J. Strojwas, "Process-Design Interaction: Modeling Based Design for Manufacturability," Tutorial, DAC, June 2003.
3. M. Lavin, "Backend CAD flows for restrictive design rules," Proc. of ICCAD, Nov 2004, pp. 739-746.
4. F. Mo, and R. Brayton, "PLA-based regular structures and their synthesis," Trans. of CAD, June 2003, pp. 723-729.
5. Y. Ran, and M. Marek-Sadowska, "Designing a via-configurable regular fabric," Proc. of CICC, 2004. pp. 423-426.
6. V. Kheterpal, et al. "Design methodology for IC manufacturability based on regular logic-bricks," Proc. of DAC, June 2005, pp. 353-358.
7. A. Koorapaty, et al. "Heterogeneous programmable logic blocks," Proc. of DATE, Mar 2003, pp. 1118-1119.
8. S. Yamashita, et al. "Pass-transistor/CMOS collaborated logic: the best of both worlds," Symp. on VLSI Circuits, June 1997.
9. G. De Micheli, Synthesis and Optimization of Digital Circuits. McGraw-Hill, 1994.
10. C. Yang, and M. Ciesielski, "BDS: a BDD-based logic optimization system," Trans. on CAD, July 2002, pp. 866-876.
11. T. Stanion, and C. Sechen, "Boolean division and factorization using binary decision diagrams," Trans. on CAD, Sept. 1994, pp. 1179-1184.
12. L. Hellerman, "A measure of computational work," Trans. on Computers, vol. c-21, May 1972.
13. http://www.synopsys.com/products/logic/design_compiler.html
14. I. Sutherland, R. Sproull, and D. Harris, Logical Effort. Academic Press, 1999.