Simulation results and formalism for global-local scheduling in semiconductor manufacturing facilities

Proceedings - Winter Simulation Conference

Volumn , Issue , 2007, Pages 1768-1773

  Bureau, Mickaël ^a   Dauzère Pérès, Stéphane ^a   Yugma, Claude ^a   Vermariën, Leon ^b   Maria, Jean Bernard ^b  

^a ECOLE DES MINES DE SAINT ETIENNE   (France)

^b STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CONDUCTIVITY; SCHEDULING; SEMICONDUCTOR MATERIALS;

CYCLE TIME; DYNAMIC ADAPTATIONS; EXPERIMENTAL TESTING; GLOBAL-LOCAL; LOCAL SCHEDULING; REAL DATA; SEMICONDUCTOR MANUFACTURING; SIMULATION RESULTS;

INDUSTRIAL APPLICATIONS;

EID: 49749120601     PISSN: 08917736     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/WSC.2007.4419801     Document Type: Conference Paper

References (6)

1. Arisha, A., P. Young, and M. El-Baradie. 2004. A simulation model to characterize the photolithography process of a semiconductor wafer fabrication. Journal of Materials Processing Technology:2071-2079.
2. Brooks-PRI Automation, Inc. 2002, October. Autosched ap 7.2 user's guide. Brooks-PRI Automation, Inc.
3. Moench, L., and I. Habenicht. 2003. Simulation-based assessment of batching heuristics in semiconductor manufacturing. 1338-1345. Winter Simulation Conference.
4. Pillai, D. D., E. L. Bass, J. C. Dempsey, and E. J. Yellig. 2004, August. 300-mm full-factory simulations for 90- and 65-nm ic manufacturing. IEEE Transactions on Semiconductor Manufacturing 17 (3): 292-298.
5. Varadarajan, A., and S. Sarin. 2006, May. A survey of dispatching rules for operational control in wafer fabrication. Volume 2, 715-726. INCOM.
6. Vialletelle, P., and G. France. 2006, May. An overview of an original wip management framework at a high volume / high mix facility. Volume Industrial supplement and discussion papers, 89-92. INCOM.