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Volumn 12, Issue PART 1, 2006, Pages

An overview of an original WIP management framework at a high volume / high mix facility

Author keywords

Dispatching; Semiconductor manufacturing; WIP management

Indexed keywords

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 79961182663     PISSN: 14746670     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.3182/20060517-3-fr-2903.00055     Document Type: Conference Paper
Times cited : (2)

References (5)
  • 1
    • 0042887637 scopus 로고    scopus 로고
    • A new scheduling approach using combined dispatching criteria in wafer fabs
    • Dabbas, R.M. and J.W. Fowler (2003). A new scheduling approach using combined dispatching criteria in wafer fabs. IEEE Transactions on semiconductor manufacturing, Vol 16, No. 3, pp. 501-510.
    • (2003) IEEE Transactions on Semiconductor Manufacturing , vol.16 , Issue.3 , pp. 501-510
    • Dabbas, R.M.1    Fowler, J.W.2
  • 2
    • 0032183805 scopus 로고    scopus 로고
    • A simulation study of dispatch rules for reducing flow times in semiconductor wafer fabrication
    • Hung, Y.F. and I.R. Chen (1998). A simulation study of dispatch rules for reducing flow times in semiconductor wafer fabrication. Production Planning and Control. Vol 9, No. 7, pp. 714-722.
    • (1998) Production Planning and Control , vol.9 , Issue.7 , pp. 714-722
    • Hung, Y.F.1    Chen, I.R.2
  • 3
    • 28644451407 scopus 로고    scopus 로고
    • Metaheuristic scheduling of 300-mm lots containing multiple orders
    • Qu, P. and S. J. Mason (2005). Metaheuristic scheduling of 300-mm lots containing multiple orders. IEEE Transactions on Semiconductor Manufacturing. Vol 18, No.4, pp.633-643.
    • (2005) IEEE Transactions on Semiconductor Manufacturing , vol.18 , Issue.4 , pp. 633-643
    • Qu, P.1    Mason, S.J.2
  • 4
    • 13844275599 scopus 로고    scopus 로고
    • Dynamic load balancing among multiple fabrication lines through estimation of minimum inter-operation time
    • Toba, H., H. Izumi, H. Hatada and T. Chikushima (2005). Dynamic load balancing among multiple fabrication lines through estimation of minimum inter-operation time. IEEE Transactions on semiconductor manufacturing. Vol 18, No. 1, pp. 202-213.
    • (2005) IEEE Transactions on Semiconductor Manufacturing , vol.18 , Issue.1 , pp. 202-213
    • Toba, H.1    Izumi, H.2    Hatada, H.3    Chikushima, T.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.