Constraint based temporal partitioning model for partial reconfigurable architectures

Proceedings - INMIC 2003: IEEE 7th International Multi Topic Conference

Volumn , Issue , 2003, Pages 242-246

  Jafri, K ^a   Jafri, N ^a   Khan, S ^a  

^a CENTER FOR ADVANCED STUDIES IN ENGINEERING   (Pakistan)

Author keywords

Application specific integrated circuits; Bifurcation; Computer aided software engineering; Cost function; Design optimization; Field programmable gate arrays; Hardware; Microprocessors; Reconfigurable architectures; Runtime

Indexed keywords

APPLICATION PROGRAMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; BIFURCATION (MATHEMATICS); COMPUTER AIDED SOFTWARE ENGINEERING; COST ENGINEERING; COST FUNCTIONS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; MAPPING; MICROPROCESSOR CHIPS; RECONFIGURABLE ARCHITECTURES; RECONFIGURABLE HARDWARE; SOFTWARE ENGINEERING;

ARCHITECTURAL CONSTRAINTS; DESIGN OPTIMIZATION; EFFICIENT IMPLEMENTATION; OBJECTIVE FUNCTIONS; PARTIAL RECONFIGURATION; PROCESSING ELEMENTS; RUNTIMES; TEMPORAL PARTITIONING;

COMPUTER HARDWARE;

EID: 49749118797     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/INMIC.2003.1416714     Document Type: Conference Paper

References (8)

1. Brebner, G. :"An interactive data sheet for the Xilinx XC6200", Field Programmable Logic: From FPGAs to Computing Paradigm (FPL98), pp 401-405, 1998.
2. Xilinx: Data book and application notes. http://www.xilinx.com.
3. Wayne Luk and I.page. "Parameterising Designs for FPGAs". In FPGAs, Abingdon EE & CS books, 1991.
4. Scott Hauck and Anant Agrawal: "Software Technologies for Reconfigurable Systems", Northwestern university, Dept. of ECE, Technical Report, 1996.
5. "Reconfigurable Computing made easy",
6. J. Spillane and H. Owen: "Temporal Partitioning for Partially Reconfigurable Field Programmable Gate", Proceedings of reconfigurable architectures Workshop (RAW 98), 1998.
7. M. Kaul and R. Vermuri, "Temporal Partioning Combined with Design Space Exploration for Latency Minimization of Run Time Reconfigured Design", Proceedings of the Date, pp 202-209, 1999.
8. K. Puma, D. Bhatia, "Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers", IEEE Trans. on Computers, vol. 48. June 1999.