A 108dB SNR 1.1mW oversampling audio DAC with a three-level DEM technique

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 488-490

  Nguyen, Khiem ^a   Bandyopadhyay, Abhishek ^a   Adams, Bob ^a   Sweetland, Karl ^a   Baginski, Paul ^a  

^a ANALOG DEVICES INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

NETWORKS (CIRCUITS); SOLID STATE DEVICES;

AUDIO DAC; CMOS PROCESSS; DEM TECHNIQUES; MULTI-BITS; OUTPUT STAGES; OVER SAMPLING; THREE-LEVEL;

SIGNAL TO NOISE RATIO;

EID: 49549091555     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523270     Document Type: Conference Paper

References (4)

1. R. Adams, K. Nguyen, K. Sweetland, "A 113dB SNR Oversampling DAC with Segmented Noise Shaped Scrambling" ISSCC Dig. Tech. Papers, pp. 62-63, Feb. 1998.
2. E. van Tuijl, J. van den Homberg, D. Reefman, et at., "A 128fs Multi-bit ΔΣ CMOS Audio DAC with Real-Time DEM and 115dB SFDR," ISSCC Dig. Tech. Papers, pp. 368-369, Feb. 2004.
3. D. Mercer, "Low Power Approaches to High Speed Current Steering Digital-to-Analog Converters in 0.18μm CMOS," IEEE J. Solid-State Circuits, vol. 42, no. 8, pp. 1688-1696, Aug. 2007.
4. K. Nguyen and R. Schreier, "System and Method for Tri-Level Logic Data Shuffling for Oversampling Data Conversion," U.S. Patent 7,079,063, Jul. 18, 2006.