Design, analysis, and optimization of DDR2 memory power delivery network

IEEE Topical Meeting on Electrical Performance of Electronic Packaging

Volumn , Issue , 2007, Pages 87-90

  Lee, Junho ^a   Kim, Hyunseok ^a   Kyung, Kimyung ^a   You, Minyoung ^a   Lee, Hyungdong ^a   Park, Kunwoo ^a   Chung, Byongtae ^a  

^a Hynix Semiconductor Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CAPACITORS; CHIP SCALE PACKAGES; CUSTOMER SATISFACTION; DIELECTRIC DEVICES; ELECTRIC CONVERTERS; ELECTRIC EQUIPMENT; ELECTRIC POWER TRANSMISSION; ELECTRONICS PACKAGING; POWER ELECTRONICS;

ANALYSIS METHODS; CHIP COSTS; DECOUPLING CAPACITORS; DESIGN PROCEDURES; MEMORY CHIPS; ON CHIPS; POWER DELIVERY NETWORKS; POWER NOISES;

ELECTRONIC EQUIPMENT MANUFACTURE;

EID: 47949130223     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPEP.2007.4387131     Document Type: Conference Paper

References (5)

1. ITRS, "International Technology Roadmap for Semiconductor,"
2. Larry D Smith, Raymond E. Anderson, Douglas W. Forehand, Thomas J. Pelc, and Tanmoy Roy, "Power Distribution System Design Methodology and Capacitor Selection for Modern CMOS Technology", IEEE Transactions on Advanced Packaging, vol. 22, no. 3, pp 284-291, August 1999
3. Gerard Villur, Eduard Alarcdn, Fraocesc Guinjoan and Alberto Poveda, "Optimized design of MOS capacitors in standard CMOS technology and evaluation of their Equivalent Series Resistnance for power applications," Proc. Of the International Symposium on Circuits and Systems, vol. 3, pp. 111-451-454, May 2003
4. Hyunjeong Park, Dong Gun Gam, Joungho Kim, and Hyungsoo Kim, "Modeling and simulation of IC and package power/ground network", IEEE International Symposium on Electromagnetic Compatibility, vol. 3, pp. 696-701 August 2006
5. JEDEC, "DDR2 SDRAM SPECIFICATION"