Hierarchical cache coherence protocol verification one level at a time through assume guarantee

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Volumn , Issue , 2007, Pages 107-114

  Chen, Xiaofang ^a   Yang, Yu ^a   Delisi, Michael ^a   Gopalakrishnan, Ganesh ^a   Chou, Ching Tsun ^b  

^a Department of Electrical and Computer Engineering   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MODEL CHECKING; STATE SPACE METHODS; TESTING;

ABSTRACT PROTOCOLS; ATOMIC TRANSACTIONS; CACHE COHERENCE PROTOCOLS; COHERENCE PROTOCOLS; ERROR PRONE; EXPLICIT STATE; EXPLICIT-STATE MODEL; HIERARCHICAL ORGANIZATIONS; HIGH LEVEL DESIGNS; INTERNATIONAL (CO); MULTI CORES; PROCESSOR DESIGNS; STATE SPACES; SYMBOLIC METHODS;

COHERENT LIGHT;

EID: 47949126252     PISSN: 15526674     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HLDVT.2007.4392796     Document Type: Conference Paper

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