Model-driven test generation for system level validation

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Volumn , Issue , 2007, Pages 83-90

  Mathaikutty, Deepak A ^a   Ahuja, Sumit ^a   Dingankar, Ajit ^b   Shukla, Sandeep ^a  

^a VIRGINIA POLYTECHNIC INSTITUTE AND STATE UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PROGRAMMING LANGUAGES; COMPUTER SOFTWARE; EMBEDDED SYSTEMS; ENERGY MANAGEMENT; INTEGRATED CIRCUITS; LINGUISTICS; MICROPROCESSOR CHIPS; SOFTWARE DESIGN; SYSTEMS ANALYSIS; TESTING;

ASSERTION-BASED VERIFICATION (ABV); CASE STUDIES; CRITICAL POWER; ESTEREL; FUNCTIONAL COVERAGE; FUNCTIONAL VALIDATION; GENERATING TEST SUITES; HIGH LEVEL DESIGNS; INTEGRATED FRAMEWORKS; INTERNATIONAL (CO); METRICS (CO); MODEL-DRIVEN; MODEL-DRIVEN DEVELOPMENT (MDD); MODIFIED CONDITION/DECISION COVERAGE (MC/DC); POWER MANAGEMENT (PM); SAFETY CRITICAL SOFTWARE SYSTEMS; STATE MACHINES; SYNCHRONOUS LANGUAGES; SYSTEM LEVELS; SYSTEM-LEVEL DESIGNS; SYSTEM-LEVEL LANGUAGES; SYSTEM-LEVEL MODELING; SYSTEMC; TEMPORAL LANGUAGES; TEST CASE GENERATION; TEST GENERATIONS;

LOGIC DESIGN;

EID: 47949095171     PISSN: 15526674     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HLDVT.2007.4392792     Document Type: Conference Paper

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