A method to measure impedance of chip/package/board power supply system using pseudo-impulse current

Electrical Performance of Electronic Packaging, EPEP

Volumn , Issue , 2006, Pages 33-36

  Zhou, Yaping ^a   Dhong, Sang H ^a   Flachs, Brian ^a   Harvey, Paul M ^a   Michael, Brad W ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLIED (CO); DIGITAL SYSTEMS; ELECTRICAL PERFORMANCES; ELECTRONIC PACKAGING; IMPULSE CURRENTS; POWER SUPPLY SYSTEMS; POWERPC; SYNCHRONOUS CLOCKING;

ELECTRIC POWER DISTRIBUTION; ELECTRIC POWER SYSTEMS; ELECTRIC POWER UTILIZATION; ELECTRONICS PACKAGING;

ELECTRIC POWER TRANSMISSION NETWORKS;

EID: 47949087109     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPEP.2006.321183     Document Type: Conference Paper

References (5)

1. I. Novak, "Probes and Setup for Measuring Power-Plane Impedances with Vector Network Analyzer," DesignCon 1999, pp.201-215, 1999.
2. I. Kantorovich, C. Houghton, S. Root, and J. Laurent, "Measurement of Low Impedance on Chip Power Supply Loop", IEEE Trans, on Adv. Packaging, 27, pp.10-14, 2004
3. th EPEP Topical Meeting, pp. 319-322, 2002.
4. A. Waizman, "CPU power supply impedance profile measurement using FFT and clock gating," IEEE 12th EPEP Topical Meeting, pp. 29-32, 2003.
5. R. Weekly, S. Chun, A. Haridass, C. O'Reilly, J. Jordan, and F. O'Connel, "Optimum Design of Power Distribution System via Clock Modulation," IEEE 12th EPEP Topical Meeting, pp. 45-48, 2003.