Upset characterization and test methodology of the PowerPC405 hard-core processor embedded in Xilinx field programmable gate arrays

IEEE Radiation Effects Data Workshop

Volumn , Issue , 2007, Pages 167-171

  Allen, Gregory R ^a,b   Swift, Gary M ^c   Miller, Greg ^c  

^a IEEE

^b CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

^c XILINX INC   (United States)

Author keywords

Field programmable gate array; Heavy ion upsets; Microprocessor faults; Single event upset

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MOSFET DEVICES; RADIATION;

FIELD PROGRAMMABLE GATE ARRAY; FIELD-PROGRAMMABLE GATE ARRAYS; HEAVY ION UPSETS; LOW THRESHOLDS; MEMORY ELEMENTS; MICROPROCESSOR FAULTS; POWERPC; PSEUDO-STATIC; SCALING TRENDS; SINGLE EVENT UPSET; SPACE RADIATIONS; TEST METHODOLOGY; VIRTEX-4; VIRTEX-II;

RADIATION EFFECTS;

EID: 47849122973     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/REDW.2007.4342559     Document Type: Conference Paper

References (16)

1. F. Irom, F. Farmanesh, et al., "Single-event upset in evolving commercial silicon-on-insulator microprocessor technologies," IEEE Trans. Nucl. Sci., vol. NS-50, no. 6, pp. 2107-2112, Dec. 2003.
2. R. Koga, W.A. Kolasinski, M.T. Marra, and W.A. Hanna, "Techniques of microprocessor testing and SEU-rate prediction," IEEE Trans. Nucl. Sci., vol. NS-32, no. 6, pp. 4219-4224, Dec. 1985.
3. F. Bezerra et al., "Commercial processor single event tests," RADECS Conf. Data Workshop Record, 1997, pp. 41-46.
4. G. Swift, F. Farmanesh, et al., "Single Event Upset in the PowerPC750 Processor," IEEE Trans. Nucl. Sci., vol. NS-47, no. 6, pp. 1822-1827, Dec. 2001.
5. C. Carmichael, "Correcting Single-Event Upsets Through Virtex Partial Configuration". Xilinx Application Note XAPP216 (v1.0). June 1, 2000.
6. C. Carmichael, "Triple Module Redundancy Design Techniques for Virtex FPGAs", Xilinx Application Note XAPP197, Nov. 2001.
7. J. George et al., "Initial Single-Event Effects Testing and Mitigation in the Xilinx Virtex II-Pro FPGA," Paper 211, MAPLD 2005.
8. J. George et. al., "Single Event Upsets in Xilinx Virtex-4 FPGA Devices," NSREC Conf. Data Workshop Record, 2006, pp. 109-114.
9. R. Koga, J. George, et al., "Comparison of Xilinx Virtex-II SEE sensitivities to protons and heavy ions," IEEE Trans. Nucl. Sci., vol. NS-51, no. 5, pp. 2825-2833, Oct. 2005.
10. P. Calvel, C. Barillot, P. Lamothe, R. Ecoffet, S. Duzellier, and D. Falguere, "An empirical model for predicting proton induced upset," IEEE Trans. Nucl. Sci., vol. NS-43, no. 6, pp. 2827-2832, 1996.
11. Larry D. Edmonds, "Proton SEU cross sections derived from heavy-ion test data," IEEE Trans. Nucl. Sci., vol 47, no. 5, 2000.
12. F. Irom, F. Farmanesh, A. Johnston, G. Swift, and D. Millward, "Single-Event Upset in Commercial Silicon-on-Insulator PowerPC Microprocessors," IEEE Trans. Nucl. Sci., vol. NS-49, no. 6, pp. 3148-3155, Dec. 2002.
13. Using Proton Irradiation," IEEE REDW Record, pp 51-56, 2005.
14. M. Wang and G. Bolotin, "SEU Mitigation Techniques for Xilinx Virtex-II Pro FPGA," Paper D110, MAPLD 2004. Available: http://klabs.org/mapld04/presentations/session_d/1_d110_wang_s.ppt
15. H.H. Ng, "PPC405 Lockstep System on ML310," Xilinx Application Note 564, Octpber 2004. Available: http://www.xilinx.com/bvdocs/appnotes/ xapp564.pdf
16. Yutao He, "smCore - Reusable SEU Mitigation Technology for FPGA-based Mitigation: Design and Implementation Documentation", JPL Document, Rev 1.1, September 2005,unpublished.