Novel agent-based management for fault-tolerance in network-on-chip

Proceedings - 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, DSD 2007

Volumn , Issue , 2007, Pages 551-555

  Rantala, Pekka ^a   Isoaho, Jouni ^a,b   Tenhunen, Hannu ^a,b  

^a UNIVERSITY OF TURKU   (Finland)

^b TURKU CENTRE FOR COMPUTER SCIENCE   (Finland)

Author keywords

Agent; Fault tolerance; Network on chip; Reconfigurability

Indexed keywords

AGENT TECHNOLOGIES; ARCHITECTURE LEVELS; CONCEPTUAL LEVELS; DATA FLOWS; MONTE CARLO SIMULATIONS; NETWORK TOPOLOGIES; NETWORK-ON-CHIP; NOC SYSTEMS; RE-CONFIGURATIONS; RECONFIGURABILITY; STUDY CASES; SYSTEM CONTROLS; SYSTEM LEVELS;

AGENTS; AUTONOMOUS AGENTS; CONTROL SYSTEMS; ELECTRIC NETWORK TOPOLOGY; FAULT TOLERANCE; FAULT TOLERANT COMPUTER SYSTEMS; MONTE CARLO METHODS; NETWORK MANAGEMENT; QUALITY ASSURANCE; RELIABILITY; SYSTEMS ANALYSIS;

ARCHITECTURAL DESIGN;

EID: 47749126939     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2007.4341523     Document Type: Conference Paper

References (18)

1. Yung-Yuan Chen, Sau-Gee Chen and Jiann-Cherng Lee, Yield and Performance Issues in Fault-Tolerant WSI Array Architectures. Wafer Scale Integration, 1995. Proceedings., Seventh Annual IEEE International Conference on 18-20 Jan. 1995 Page(s):318-328
2. R. C. Aubusson and I. Catt, Wafer scale integration: A new approach. in 3rd European Solid-State Cir. Conj Dig., Sept. 1977, pp. 76-78.
3. Sami M., Stefanelli R. Reconfigurable Architectures for VLSI Processing Arrays. Proc. of IEEE 1986
4. M Chean, J Fortes, A Taxonomy of Reconfiguration Techniques for Fault-Tolerant Processor Arrays. Proc. of IEEE 1990
5. International Technology Roadmap for Semiconductors 2005. (http://public.itrs.net).
6. Barry W. Johnson, Design and Analysis of Fault-Tolerant Digital Systems,. Addison-Wesley Publishing Company, 1989
7. Maurizio (ed.) Valle, Smart Adaptive Systems on Silicon. Springer, 2004
8. C Constantinescu, Trends and challenges in VLSI circuit reliability. Micro, IEEE, 2003
9. M Chean, J Fortes, Fault Tolerance in Highly Parallel Mesh-Connected Processors. Computer, 1990
10. Nurmi, J.; Tenhunen, H.; Isoaho, J.; Jantsch, A. (Eds.) Interconnect-Centric Design for Advanced SOC and NOC. 2004, VII, 453 p.
11. Benini, De Micheli, Networks on Chips: Technology and Tools. Morgan Kaufmann Publishers Inc,US, 2006
12. A. Aggarwal and M. Franklin An Empirical Study of the Scalability Aspects of Instruction Distribution Algorithms for Clustered Processors. Proc. International Symp. on Performance Analysis of Systems and Software (ISPASS 01), 2001.
13. A. Jantsch and H. Tenhunen (Eds.), Networks on Chip. Kluwer Academic Publishers, 2003
14. K. Goossens, Guaranteeing the quality of services in Networks on a Chip. p. 61-82, Kluwer Academic Publishers, 2003
15. M. Hannebauer, Autonomous Dynamic Reconfiguration in Multi-Agent Systems. Springer, 2002
16. Russell S, Norvig P, Artificial Intelligence: A Modern Approach. Prentice Hall Series in Artificial Intelligence. Englewood Cliffs, New Jersey, 1995
17. Pekka Rantala, Teijo Lehtonen, Jouni Isoaho and Juha Plosila Fault-tolerant Routing Approach for Reconfigurable Networks-on-Chip. in the Proceedings of International Symposium on System-on-Chip, Tampere, Finland, November 13-16, 2006
18. Pekka Rantala, Jouni Isoaho, Hannu Tenhunen, Agent-Based Reconfigurability for Fault-Tolerance in Network-on-Chip. in the Proceedings of International Conference on Engineering of Reconfigurable Systems and Algorithms, Las Vegas, Nevada, USA, June 25-28, 2007