An HDL-based platform for high level NoC switch testing

Proceedings of the Asian Test Symposium

Volumn , Issue , 2007, Pages 453-458

  Sedghi, Mahshid ^a   Alaghi, Armin ^a   Koopahi, Elnaz ^a   Navabi, Zainalabedin ^a  

^a UNIVERSITY OF TEHRAN   (Iran)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; COMPUTER HARDWARE DESCRIPTION LANGUAGES; ELECTRIC NETWORK TOPOLOGY; ERROR DETECTION; FAULT DETECTION; SWITCHES;

FAULT MODELING; NOC SWITCH; PROCESSING ELEMENTS; RUNNING-IN; SCAN METHODS; TEST ENVIRONMENT; TEST STRATEGIES;

TESTING;

EID: 47649130908     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2007.4388053     Document Type: Conference Paper

References (10)

1. A Cristian Grecu, André Ivanov, Res Saleh, Egor S. Sogomonyan, Partha Pratim Pande, "On-line Fault Detection and Location for NoC Interconnects", Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS'06), 2006.
2. Xuan-Tu TRAN, Jean DURUPT, Francois BERTRAND, Vincent BEROULLE, Chantal ROBACH, "A DFT Architecture for Asynchronous Networks-on-Chip", Proceedings of the Eleventh IEEE European Test Symposium (ETS'06), 2006.
3. Mohammad Hosseinabadi, Atefe Dalirsani, Zainalabedin Navabi, "Using the Inter- and Intra-Switch Regularity in NoC Switch Testing", Proceedings of Design Automation and Test in Europe 2007.
4. Tomas Bengtsson, Shashi Kumar and Zebo Peng, "Application Area Specific System Level Fault Models: A Case Study with a Simple NoC Switch", Proceedings (electronic) of International Design and Test Workshop (IDT) Dubai, United Arab Emirates, November 2006.
5. Mohammad Hosseinabady, Abbas Banaiyan, Mahdi Nazm Bojnordi, Zainalabedin Navabi, "A concurrent testing method for NoC switches", DATE 2006: 1171-1176.
6. Ming Li, Wen-Ben Jone, Qing-An Zeng, "An Efficient Wrapper Scan Chain Configuration Method for Network-on-Chip Testing", Proceedings of the 2006 Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006.
7. Cristian Grecu, Partha Pande, André Ivanov, Res Saleh, "BIST for Network-on-Chip Interconnect Infrastructures", Proceedings of the 24th IEEE VLSI Test Symposium (VTS'06), 2006.
8. A. M. Amory, E. Brião, É. Cota, M. ubaszewski, F.G. Moraes, "A Scalable Test Strategie for Networkon-Chip Routers", Proceedings of ITC, 2005.
9. Jaan Raik, Vineeth Govind, Raimund Ubar, "An External Test Approach for Network-on-a-Chip Switches", 15th Asian Test Symposium (ATS'06), 2006.
10. Atefe Dalirsani, Mohammad Hosseinabadi, Zainalabedin Navabi, "An Analytical Model for Reliability Evaluation of NoC Architectures", To appear in Proceedings of International On-Line Testing Symposium 2007.