A module checking based converter synthesis approach for SoCs

Proceedings of the IEEE International Frequency Control Symposium and Exposition

Volumn , Issue , 2008, Pages 492-499

  Sinha, Roopak ^a   Roop, Partha S ^a   Basu, Samik ^b  

^a UNIVERSITY OF AUCKLAND   (New Zealand)

^b Iowa State University

Author keywords

Module checking; Protocol conversion; Protocol mismatches

Indexed keywords

AUTOMATICALLY GENERATED; CONTROL COMMUNICATIONS; CONVERTER SYNTHESIS; FORMAL SETTING; INTERNATIONAL CONFERENCES; MODULE CHECKING; PROTOCOL CONVERSION; SYSTEM-LEVEL SPECIFICATIONS; VLSI DESIGNS; WIDE-RANGE;

FUZZY LOGIC; SPECIFICATIONS;

TEMPORAL LOGIC;

EID: 47649099011     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSI.2008.109     Document Type: Conference Paper

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