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Volumn , Issue , 2007, Pages 263-266

Design for 3D integration and applications

Author keywords

3D IC; CAD; VLSI

Indexed keywords

COMPUTER AIDED DESIGN;

EID: 47349132917     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSSE.2007.4294463     Document Type: Conference Paper
Times cited : (11)

References (14)
  • 3
    • 33747566850 scopus 로고    scopus 로고
    • 3-D ICs: A Novel Chip Design For Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration
    • K. Banerjee, S. Souri, P. Kapur, K. Saraswat, "3-D ICs: A Novel Chip Design For Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration," Proc. IEEE, Vol. 89, No. 5, 2001.
    • (2001) Proc. IEEE , vol.89 , Issue.5
    • Banerjee, K.1    Souri, S.2    Kapur, P.3    Saraswat, K.4
  • 5
    • 2942658001 scopus 로고    scopus 로고
    • Timign, Energy and Tehrmal Performance of Three Dimensional Integratied Circuits
    • S. Das, A. Chandrakasan, R. Reif, "Timign, Energy and Tehrmal Performance of Three Dimensional Integratied Circuits," Proc. Great Lakes Symposium on VLSI, pp.338-343, 2004.
    • (2004) Proc. Great Lakes Symposium on VLSI , pp. 338-343
    • Das, S.1    Chandrakasan, A.2    Reif, R.3
  • 6
    • 4544293938 scopus 로고    scopus 로고
    • Future Microprocessors and off-chip SOP Interconnect
    • May
    • H.P Hofstee, "Future Microprocessors and off-chip SOP Interconnect," in IEEE Trans. Advanced Packaging, Vol. 27, No. 2, May 2004, pp. 301-303.
    • (2004) IEEE Trans. Advanced Packaging , vol.27 , Issue.2 , pp. 301-303
    • Hofstee, H.P.1
  • 7
    • 47349085507 scopus 로고    scopus 로고
    • Design and Verification Methodology for Complex Three-Dimensional Digital Integrated Circuits,
    • Ph.D. Dissertation, NC State University, Under the direction of Dr. W.R. Davis
    • H. Hua, "Design and Verification Methodology for Complex Three-Dimensional Digital Integrated Circuits," Ph.D. Dissertation, NC State University, 2006. Under the direction of Dr. W.R. Davis.
    • (2006)
    • Hua, H.1
  • 8
    • 0030290949 scopus 로고    scopus 로고
    • Performance Modeling of the Interconnect Structfure ofa Three-Dimensional Integrated RISC Processor/Cache System
    • Part B, Nov
    • S.A. Kuhn, M.B. Kleiner, P. Ramm, W. Weber, "Performance Modeling of the Interconnect Structfure ofa Three-Dimensional Integrated RISC Processor/Cache System," IEEE Trans. CPMT, Part B, Vol.19, No.4, Nov, 1996, pp. 719-727.
    • (1996) IEEE Trans. CPMT , vol.19 , Issue.4 , pp. 719-727
    • Kuhn, S.A.1    Kleiner, M.B.2    Ramm, P.3    Weber, W.4
  • 10
    • 84938579900 scopus 로고    scopus 로고
    • Design Considerations and benefits of Three-Dimensional Ternary Content Addressable Memory
    • Oct
    • E.C. Oh, P.D. Franzon, "Design Considerations and benefits of Three-Dimensional Ternary Content Addressable Memory," Proc. IEEE CICC, Oct., 2007.
    • (2007) Proc. IEEE , vol.299
    • Oh, E.C.1    Franzon, P.D.2
  • 11
    • 84962920831 scopus 로고    scopus 로고
    • A. Rahman, . Fan, R. Reif, Comparison of Key Performance Metrics in Two and Three Dimensional Interrgated Circuits, Proc. Int. Interconnect Technology Conference, pp. 18-20, 2000.
    • A. Rahman, . Fan, R. Reif, "Comparison of Key Performance Metrics in Two and Three Dimensional Interrgated Circuits," Proc. Int. Interconnect Technology Conference, pp. 18-20, 2000.
  • 12
    • 0037312415 scopus 로고    scopus 로고
    • Wiring Requirement and Three-Dimensional Integration Technology for Field Programmable Gate Arrays
    • «, », Feb
    • A. Rahman, S. Das, A. Chandrakasan, R. Reif, « Wiring Requirement and Three-Dimensional Integration Technology for Field Programmable Gate Arrays, » IEEE Trans. VLSI, Vol. 11, No. 1, Feb, 2003, pp. 44-54.
    • (2003) IEEE Trans. VLSI , vol.11 , Issue.1 , pp. 44-54
    • Rahman, A.1    Das, S.2    Chandrakasan, A.3    Reif, R.4
  • 13
    • 47349103433 scopus 로고    scopus 로고
    • Performance Analsysi of System-on-Chip Application of 3D Integrated Circuits,
    • MS. Thesis, NC State University. Under direction of Dr. W.R. Davis
    • K. Schoenfliess, "Performance Analsysi of System-on-Chip Application of 3D Integrated Circuits," MS. Thesis, NC State University. Under direction of Dr. W.R. Davis.
    • Schoenfliess, K.1
  • 14
    • 47349111522 scopus 로고    scopus 로고
    • www.tezzaron.com


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.