A Fast VLSI Adder Architecture

IEEE Journal of Solid-State Circuits

Volumn 27, Issue 5, 1992, Pages 761-767

  Srinivas, H R ^a   Parhi, Keshab K ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; COMPUTER SYSTEMS, DIGITAL - PARALLEL PROCESSING; COMPUTERS, DIGITAL - ADDERS; INTEGRATED CIRCUITS, VLSI; REDUNDANCY;

RADIX-2 REDUNDANT ADDER; REDUNDANT-TO-BINARY CONVERSION; SIGN-SELECT OPERATION; TWO'S COMPLEMENT ADDITION; VLSI ADDER ARCHITECTURE;

MICROPROCESSOR CHIPS;

EID: 0026867592     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.133165     Document Type: Article

References (8)

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