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Volumn , Issue , 2006, Pages 818-821

Ultra low voltage CMOS gates

Author keywords

[No Author keywords available]

Indexed keywords

CMOS GATES; INTERNATIONAL CONFERENCES; SUPPLY VOLTAGES; ULTRA-LOW VOLTAGE;

EID: 47349086154     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2006.379914     Document Type: Conference Paper
Times cited : (22)

References (9)
  • 3
    • 0029359285 scopus 로고
    • 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS
    • Aug, Pages
    • Mutoh S., Douseki T., Matsuya Y., Aoki T., Shigematsu S., Yamada J.: "1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS" IEEE Journal of Solid-State Circuits, Volume 30, Issue 8, Aug. 1995 Page(s):847 - 854
    • (1995) IEEE Journal of Solid-State Circuits , vol.30 , Issue.8 , pp. 847-854
    • Mutoh, S.1    Douseki, T.2    Matsuya, Y.3    Aoki, T.4    Shigematsu, S.5    Yamada, J.6
  • 4
    • 0032635654 scopus 로고    scopus 로고
    • Ultra Low-Voltage/Low-Power Digital Floating-Gate Circuits
    • july
    • Y Berg, D. T. Wisland and T. S. Lande: "Ultra Low-Voltage/Low-Power Digital Floating-Gate Circuits", IEEE Transactions on Circuits and Systems, vol. 46, No. 7, pp. 930-936,july 1999.
    • (1999) IEEE Transactions on Circuits and Systems , vol.46 , Issue.7 , pp. 930-936
    • Berg, Y.1    Wisland, D.T.2    Lande, T.S.3
  • 5
    • 0029253825 scopus 로고    scopus 로고
    • K. Kotani, T. Shibata, M. Imai and T. Ohmi. Clocked-Neuron-MOS Logic Circuits Employing Auto-Threshold-Adjustment, In IEEE International Solid-State Circuits Conference (ISSCC), pp. 320-321,388, 1995.
    • K. Kotani, T. Shibata, M. Imai and T. Ohmi. "Clocked-Neuron-MOS Logic Circuits Employing Auto-Threshold-Adjustment", In IEEE International Solid-State Circuits Conference (ISSCC), pp. 320-321,388, 1995.
  • 6
    • 0032218405 scopus 로고    scopus 로고
    • R. Lashevsky, K. Takaara and M. Souma Neuron MOSFET as a Way to Design a Threshold Gates with the Threshold and Input Weights Alterable in Real Time, IEEE TT13.11-1.4, 1998, pp. 263-266.
    • R. Lashevsky, K. Takaara and M. Souma "Neuron MOSFET as a Way to Design a Threshold Gates with the Threshold and Input Weights Alterable in Real Time", IEEE TT13.11-1.4, 1998, pp. 263-266.
  • 7
    • 27944492851 scopus 로고
    • A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations
    • T. Shibata and T. Ohmi. " A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations", In IEEE Transactions on Electron Devices, vol 39, 1992.
    • (1992) In IEEE Transactions on Electron Devices , vol.39
    • Shibata, T.1    Ohmi, T.2
  • 8
    • 0035043074 scopus 로고    scopus 로고
    • Y Berg, Tor S. Lande and Ø. Nasss. Programming Floating-Gate Circuits with UV-Activated Conductances, IEEE Transactions on Circuits and Systems -11: Analog and Digital Signal Processing, 48, no. 1,pp 12-19, 2001.
    • Y Berg, Tor S. Lande and Ø. Nasss. "Programming Floating-Gate Circuits with UV-Activated Conductances", IEEE Transactions on Circuits and Systems -11: Analog and Digital Signal Processing, vol 48, no. 1,pp 12-19, 2001.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.