-
1
-
-
0026853681
-
Low-power CMOS digital design
-
April Pages
-
Chandrakasan A.P. Sheng S. Brodersen R.W.: "Low-power CMOS digital design" , IEEE Journal of Solid-State Circuits, Volume 27, Issue 4, April 1992 Page(s):473 - 484
-
(1992)
IEEE Journal of Solid-State Circuits
, vol.27
, Issue.4
, pp. 473-484
-
-
Chandrakasan, A.P.1
Sheng, S.2
Brodersen, R.W.3
-
3
-
-
0029359285
-
1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS
-
Aug, Pages
-
Mutoh S., Douseki T., Matsuya Y., Aoki T., Shigematsu S., Yamada J.: "1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS" IEEE Journal of Solid-State Circuits, Volume 30, Issue 8, Aug. 1995 Page(s):847 - 854
-
(1995)
IEEE Journal of Solid-State Circuits
, vol.30
, Issue.8
, pp. 847-854
-
-
Mutoh, S.1
Douseki, T.2
Matsuya, Y.3
Aoki, T.4
Shigematsu, S.5
Yamada, J.6
-
4
-
-
0032635654
-
Ultra Low-Voltage/Low-Power Digital Floating-Gate Circuits
-
july
-
Y Berg, D. T. Wisland and T. S. Lande: "Ultra Low-Voltage/Low-Power Digital Floating-Gate Circuits", IEEE Transactions on Circuits and Systems, vol. 46, No. 7, pp. 930-936,july 1999.
-
(1999)
IEEE Transactions on Circuits and Systems
, vol.46
, Issue.7
, pp. 930-936
-
-
Berg, Y.1
Wisland, D.T.2
Lande, T.S.3
-
5
-
-
0029253825
-
-
K. Kotani, T. Shibata, M. Imai and T. Ohmi. Clocked-Neuron-MOS Logic Circuits Employing Auto-Threshold-Adjustment, In IEEE International Solid-State Circuits Conference (ISSCC), pp. 320-321,388, 1995.
-
K. Kotani, T. Shibata, M. Imai and T. Ohmi. "Clocked-Neuron-MOS Logic Circuits Employing Auto-Threshold-Adjustment", In IEEE International Solid-State Circuits Conference (ISSCC), pp. 320-321,388, 1995.
-
-
-
-
6
-
-
0032218405
-
-
R. Lashevsky, K. Takaara and M. Souma Neuron MOSFET as a Way to Design a Threshold Gates with the Threshold and Input Weights Alterable in Real Time, IEEE TT13.11-1.4, 1998, pp. 263-266.
-
R. Lashevsky, K. Takaara and M. Souma "Neuron MOSFET as a Way to Design a Threshold Gates with the Threshold and Input Weights Alterable in Real Time", IEEE TT13.11-1.4, 1998, pp. 263-266.
-
-
-
-
7
-
-
27944492851
-
A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations
-
T. Shibata and T. Ohmi. " A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations", In IEEE Transactions on Electron Devices, vol 39, 1992.
-
(1992)
In IEEE Transactions on Electron Devices
, vol.39
-
-
Shibata, T.1
Ohmi, T.2
-
8
-
-
0035043074
-
-
Y Berg, Tor S. Lande and Ø. Nasss. Programming Floating-Gate Circuits with UV-Activated Conductances, IEEE Transactions on Circuits and Systems -11: Analog and Digital Signal Processing, 48, no. 1,pp 12-19, 2001.
-
Y Berg, Tor S. Lande and Ø. Nasss. "Programming Floating-Gate Circuits with UV-Activated Conductances", IEEE Transactions on Circuits and Systems -11: Analog and Digital Signal Processing, vol 48, no. 1,pp 12-19, 2001.
-
-
-
-
9
-
-
0038420740
-
Novel Recharge Semi-Floating-Gate CMOS Logic for Multiple-Valued Systems
-
Bangkok, may
-
Y. Berg, S. Aunet, O. Mirmotahari and M. Høvin. "Novel Recharge Semi-Floating-Gate CMOS Logic for Multiple-Valued Systems", In IEEE International Symposium on Circuits and Systems (ISCAS), Bangkok, may 2003.
-
(2003)
IEEE International Symposium on Circuits and Systems (ISCAS)
-
-
Berg, Y.1
Aunet, S.2
Mirmotahari, O.3
Høvin, M.4
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