Low power design of high performance memory access architecture for HDTV decoder

Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, ICME 2007

Volumn , Issue , 2007, Pages 699-702

  Wang, Tsun Hsien ^a   Chiu, Ching Te ^b  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

^b NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

Macroblock (MB); Memory address mapping; Memory controller; Video decoder

Indexed keywords

DECODING; ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY EFFICIENCY; ERROR CORRECTION; HIGH DEFINITION TELEVISION; IMAGE QUALITY; MAPPING; MOTION COMPENSATION;

ADDRESS GENERATION; CONVENTIONAL APPROACH; LOW-POWER DESIGN; MACRO BLOCK; MEMORY ADDRESS MAPPING; MEMORY CONTROLLER; PROGRESSIVE SCANNING; VIDEO DECODERS;

MEMORY ARCHITECTURE;

EID: 46449105591     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/icme.2007.4284746     Document Type: Conference Paper

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