Array address translation for SDRAM-based video processing applications

Electronics Letters

Volumn 35, Issue 22, 1999, Pages 1929-1931

  Kim, Hansoo ^a   Park, In Cheol ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BANDWIDTH; COMPUTER SIMULATION; IMAGE CODING; VIDEO SIGNAL PROCESSING;

ARRAY ADDRESS TRANSLATION; VIDEO PROCESSING;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0033355034     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19991300     Document Type: Article

References (3)

1. TAKAI, Y., NAGASE, M., KITAMURA, M., KOSHIKAWA, Y., YOSHIDA, N., KOBAYASHI, Y., OBARA, T., FUKUZO, Y., and WATANABE, H.: '250 Mbyte/s synchronous DRAM using a 3-stage-pipelined architecture', IEEE J. Solid-State Circuits, 1994, SSC-29, (4), pp. 426-431
2. KHARE, A., RANJAN PANDA, P., DUTT, N.D., and NICOLAU, A.: 'High-level synthesis with synchronous and RAMBUS DRAMs', Proc. Workshop Synthesis and System Integration of Mixed Technologies, October 1998, pp. 186-193
3. 'Generic coding of moving pictures and associated audio information: Video'. ISO/IEC 13818-2: Draft International Standard, November 1993