Reducing the impact of the memory wall for I/O using cache injection

Proceedings - 15th Annual IEEE Symposium on High-Performance Interconnects, HOT Interconnects

Volumn , Issue , 2007, Pages 143-149

  León, Edgar A ^a   Ferreira, Kurt B ^a   Maccabe, Arthur B ^a  

^a MSC01 1070   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION PERFORMANCE; DATA PREFETCHING; DATA USAGE; MEMORY BOUND APPLICATIONS; MEMORY CONTROLLERS; MEMORY LATENCIES; MEMORY PRESSURE; MEMORY SPEEDS; MEMORY WALL; SCIENTIFIC COMPUTATIONS;

CACHE MEMORY; COMPUTER GRAPHICS; CRYPTOGRAPHY; DATA STORAGE EQUIPMENT; GRAPHIC METHODS; IMAGE PROCESSING; IMAGING SYSTEMS; OPTICAL DATA PROCESSING; PRESSURE; PROGRAM COMPILERS;

DATA REDUCTION;

EID: 46449101559     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HOTI.2007.8     Document Type: Conference Paper

References (21)

1. H. Abdel-Shafi, J. Hall, S. V. Adve, and V. S. Adve. An evaluation of fine-grain producer-initiated communication in cache-coherent multiprocessors. In 3rd IEEE Symposium on High-Performance Computer Architecture (HPCA '97), pages 204-215, San Antonio, TX, 1997.
2. P. Bohrer, M. Elnozahy, A. Gheith, C. Lefurgy, T. Nakra, J. Peterson, R. Rajamony, R. Rockhold, H. Shafi, R. Simpson, E. Speight, K. Sudeep, E. V. Hensbergen, and L. Zhang. Mambo - a full system simulator for the PowerPC architecture. ACM SIGMETRICS Performance Evaluation Review, 31(4):8-12, Mar. 2004.
3. P. Bohrer, R. Rajamony, and H. Shafi. Method and apparatus for accelerating Input/Output processing using cache injections, Mar. 2004. US PatentNo. US 6,711,650 B1.
4. P. N. Brown, R. D. Falgout, and J. E. Jones. Semicoarsening multigrid on distributed memory machines. SIAM Journal on Scientific Computing, 21(5):1823-1834, 2000.
5. G. T. Byrd and M. J. Flynn. Producer-consumer communication in distributed shared memory multiprocessors. Proceedings of the IEEE, 87(3):456-466, 1999.
6. M. P. I. Forum. MPI: A message-passing interface standard. Technical Report UT-CS-94-230, Knoxville, TN, 1994.
7. F. R. Gantmacher. The Theory of Matrices, volume I. AMS Chelsea, 1959. Translated from Russian.
8. B. Gibbs, B. Atyam, F. Berres, B. Blanchard, L. Castillo, P. Coelho, N. Guerin, L. Liu, C. D. Maciel, C. Sosa, and R. Thirumalai. Advanced POWER Virtualization on IBM eServer p5 Servers: Architecture and Performance Considerations. IBM Redbooks, second edition, 2005.
9. R. Huggahalli, R. Iyer, and S. Tetrick. Direct cache access for high bandwidth network I/O. In 32nd Annual International Symposium on Computer Architecture (ISCA'05), pages 50-59, Madison, WI, June 2005.
10. C. Kim, D. Burger, and S. W. Keckler. An adaptive, nonuniform cache structure for wire-delay dominated on-chip caches. In 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS X), pages 211-222, San Jose, CA, Oct. 2002.
11. D. Lenoski, J. Laudon, K. Gharachorloo, W.-D. Weber, A. Gupta, J. Hennessy, M. Horowitz, and M. S. Lam. The Stanford Dash multiprocessor. Computer, 25(3):63-79, 1992.
12. E. A. León and A. B. Maccabe. Reducing memory bandwidth for chip-multiprocessors using cache injection. In 7th USENIX Symposium on Operating Systems Design and Implementation (OSDI'06). Poster Session, Seattle, WA, Nov. 2006.
13. E. A. León and M. Ostrowski. An infrastructure for the development of kernel network services. In 20th ACM Symposium on Operating Systems Principles (SOSP'05). Poster Session, Brighton, United Kingdom, Oct. 2005. ACM SIGOPS.
14. S. A. McKee, S. A. Moyer, and W. A. Wulf. Increasing memory bandwidth for vector computations. In International Conference on Programming Languages and System Architectures, pages 87-104, Zurich, Switzerland, Mar. 1994.
15. A. Milenkovic and V. Milutinovic. Cache injection on bus based multiprocessors. In 17th Symposium on Reliable Distributed Systems (SRDS'98), pages 341-346, West Lafayette, IN, 1998.
16. T. Mowry and A. Gupta. Tolerating latency through software-controlled prefetching in shared-memory multiprocessors. Journal of Parallel and Distributed Computing, 12(2):87-106, 1991.
17. S. A. Moyer. Access Ordering and Effective Memory Bandwidth. PhD thesis, Department of Computer Science, University of Virginia, Apr. 1993.
18. D. K. Poulsen and P.-C. Yew. Data prefetching and data forwarding in shared memory multiprocessors. In International Conference on Parallel Processing (ICPP'94), pages 276-280, North Carolina State University, NC, 1994.
19. B. Sinharoy, R. N. Kalla, J. M. Tendler, R. J. Eickemeyer, and J. B. Joyner. POWER5 system microarchitecture. IBM Journal of Research and Development, 49(4/5), 2005.
20. J. S. Vetter and A. Yoo. An empirical performance evaluation of scalable scientific applications. In 2002 ACM/IEEE Conference on Supercomputing (SC'02), pages 1-18, Baltimore, Maryland, 2002.
21. W. A. Wulf and S. A. McKee. Hitting the memory wall: Implications of the obvious. ACM SIGARCH Computer Architecture News, 3(1):20-24, Mar. 1995.