A tool for automatic detection of deadlock in wormhole networks on chip

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Volumn , Issue , 2006, Pages 203-210

  Taktak, Sami ^a   Encrenaz, Emmanuelle ^b   Desbarbieux, Jean Lou ^a  

^a UNIVERSITÉ PIERRE ET MARIE CURIE   (France)

^b CNRS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC DETECTION; DEADLOCK-FREENESS; HIGH LEVEL DESIGNS; IN ORDER; INTERNATIONAL (CO); LARGE SCALE NETWORKS; ORIGINAL ALGORITHMS; PROTOTYPE TOOLS; ROUTING FUNCTIONS; SUFFICIENT CONDITIONS; SUPPORT ENVIRONMENT; WORMHOLE NETWORKS;

MICROPROCESSOR CHIPS; ROUTING ALGORITHMS; TESTING;

FUNCTION EVALUATION;

EID: 46249124248     PISSN: 15526674     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HLDVT.2006.319992     Document Type: Conference Paper

References (14)

1. W. J. Dally and B. Towles, "Route Packets, Not Wires: On-Chip Interconnection Networks." in DAC. ACM, 2001, pp. 684-689.
2. L. M. Ni and P. K. McKinley, "A Survey of Wormhole Routing Techniques in Direct Networks," Computer, vol. 26, no. 2, pp. 62-76, 1993.
3. W. J. Dally and C. L. Seitz, "Deadlock-free message routing in multiprocessor interconnection networks," IEEE Trans. Compta., vol. 36, no. 5, pp. 547-553, 1987.
4. J. Duato, "A Necessary and Sufficient Condition for Deadlock-Free Adaptive Routing in Wormhole Networks," IEEE Trans. Parallel Distrib. Syst., vol. 6, no. 10, pp. 1055-1067, 1995.
5. A. A. Chien, "A Cost and Speed Model for k-ary n-Cube Wormhole Routers," IEEE Trans. Parallel Distrib. Syst., vol. 9, no. 2, pp. 150-162, 1998.
6. E. Fleury and P. Fraigniaud, "A General Theory for Deadlock Avoidance in Wormhole-Routed Networks," IEEE Trans. Parallel Distrib. Syst., vol. 9, no. 7, pp. 626-638, 1998.
7. L. Schwiebert and D. N. Jayasimha, "A Necessary and Sufficient Condition for Deadlock-Free Wormhole Routing," Journal of Parallel and Distributed Computing, vol. 32, no. 1, pp. 103-117, 1996.
8. D. N. Jayasimha, L. Schwiebert, D. Manivannan, and J. A. May, "A foundation for designing deadlock-free routing algorithms in wormhole networks," J. ACM, vol. 50, no. 2, pp. 250-275, 2003.
9. H. Charlery, A. Greiner, E. Encrenaz, L. Mortiez, and A. Andriahante-naina, "Using VCI in a on-chip system around SPIN network," in 11th International Conference Mixed Design of Integrated Circuits and Systems, 2004, pp. 571-576.
10. J. Duato, "On the Design of Deadlock-Free Adaptive Routing Algorithms for Multicomputers: Design Methodologies." vol. 505, pp. 390-405, 1991.
11. X. Lin, P. K. McKinley, and L. M. Ni, "The Message Flow Model for Routing in Wormhole-Routed Networks." IEEE Transactions on Parallel and Distributed Systems, vol. 6, no. 7, pp. 755-760, 1995.
12. M. D. Ianni, "Wormhole Deadlock Prediction." in Euro-Par, ser. Lecture Notes in Computer Science, C. Lengauer, M. Griebl, and S. Gorlatch, Eds., vol. 1300. Springer, 1997, pp. 188-195.
13. "DSPIN." [Online]. Available: http://www.lip6.fr/Direction/ 2005-05-13-DSPIN.pdf
14. P. Guerrier and A. Greiner, "A Generic Architecture for On-Chip Packet-Switched Interconnections." in DATE. IEEE Computer Society, 2000, pp. 250-256.