A layer model for systematically designing dynamically reconfigurable systems

Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL

Volumn , Issue , 2006, Pages 547-552

  Kettelhoit, Boris ^a   Porrmann, Mario ^a  

^a UNIVERSITY OF PADERBORN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; DYNAMIC MODELS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FUZZY LOGIC; INTEGRATED CIRCUITS;

DESIGN METHODOLOGIES; DYNAMIC RECONFIGURATIONS; DYNAMICALLY RECONFIGURABLE SYSTEMS (DRS); EXISTING SYSTEMS; FIELD PROGRAMMABLE LOGIC (FPL); INTERNATIONAL CONFERENCES; LAYER MODEL; RECONFIGURABLE HARDWARE (RH); SYSTEM DESIGNS; SYSTEM-ON-CHIP IMPLEMENTATIONS;

STRUCTURAL DESIGN;

EID: 46249121635     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2006.311265     Document Type: Conference Paper

References (9)

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2. C. Bobda, M. Majer, A. Ahmadinia, T. Haller, A. Linarth, J. Teich, and J. van der Veen, "The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform", In Proceedings of the 2005 IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, USA, pp. 319-320, April 17-20,2005.
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6. N. P. Sedcole, B. Blodget, T. Becker, J. Anderson, and P. Lysaght, "Modular Partial Reconfiguration in Virtex FPGAs", In Proceedings of the 2005 International Conference on Field Programmable Logiv and Applications (FPL), Tampere, Finland, pp. 211-216, August 24-26, 2005.
7. H. Kalte and M. Porrmann, "Context Saving and Restoring for Multitasking in Reconfigurable Systems", In In Proceedings of the 2005 International Conference on Field Programmable Logiv and Applications (FPL), Tampere, Finnland, pp. 223-228, August 24-26, 2005.
8. H. Kalte, M. Porrmann, and U. Rückert, "A Prototyping Platform for Dynamically Reconfigurable System on Chip Designs", IEEE Workshop Heterogeneous reconfigurable Systems on Chip (SoC), Hamburg, Germany, 2002.
9. Silicore Corp., "Wishbone System-on-Chip (SoC) Interconnection Architecture for portable IP cores", B.3 Edition, September, 2002.