A 200-MHz CMOS mixed-mode sample-and-hold circuit for pipelined ADCs

IFIP VLSI-SoIC 2006 - IFIP WG 10.5 International Conference on Very Large Scale Integration and System-on-Chip

Volumn , Issue , 2006, Pages 352-356

  Jiang, Shan ^a   Do, Manh Anh ^a   Yeo, Kiat Seng ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CIRCUIT THEORY; CMOS INTEGRATED CIRCUITS; DIGITAL ARITHMETIC; DIGITAL TO ANALOG CONVERSION; ELECTRIC CURRENTS; ENERGY STORAGE; ERROR CORRECTION; INTEGRATED CIRCUITS; LSI CIRCUITS; NETWORKS (CIRCUITS); PROGRAMMABLE LOGIC CONTROLLERS;

ANALOG TO DIGITAL CONVERTER (ADC); CMOS TECHNOLOGIES; DIGITAL ERROR CORRECTION; HIGH SPEEDS; HIGH-FREQUENCY (HF); INTERNATIONAL CONFERENCES; MIXED MODES; OUTPUT SIGNAL SWING; PIPELINED ADCS; POWER CONSUMPTION (CE); S/H CIRCUITS; SAMPLE-AND-HOLD (S/H) CIRCUITS; SAMPLE-AND-HOLD (SHA); SAMPLED DATA; SUPPLY VOLTAGES; SWITCHED CAPACITOR (SC); SYSTEM ON CHIP (SOCS); TIME CONSTANTS (TC); TOTAL HARMONIC DISTORTION (TDH); VERY LARGE SCALE INTEGRATION (VLSI); WORST CASE;

ANALOG TO DIGITAL CONVERSION;

EID: 46249120104     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSISOC.2006.313260     Document Type: Conference Paper

References (7)

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