-
2
-
-
0013417553
-
The next generation of Intel IXP network processors
-
Intel Communications Group, Intel Corporation, Aug
-
Matthew Adiletta, Mark Rosenbluth, Debra Bernstein, Gilbert Wolrich, and Hugh Wilkinson. The next generation of Intel IXP network processors. In INTEL technology journal, volume 6, Intel Communications Group, Intel Corporation, Aug 2002.
-
(2002)
INTEL technology journal
, vol.6
-
-
Adiletta, M.1
Rosenbluth, M.2
Bernstein, D.3
Wolrich, G.4
Wilkinson, H.5
-
3
-
-
46249093125
-
JAHUEL: A formal framework for software synthesis
-
I. Assayad, V. Bertin, F-X. Defaut, Ph. Gerner, O. Quévreux, and S. Yovine. JAHUEL: A formal framework for software synthesis. In ICFEM'05, 2005.
-
(2005)
ICFEM'05
-
-
Assayad, I.1
Bertin, V.2
Defaut, F.-X.3
Gerner, P.4
Quévreux, O.5
Yovine, S.6
-
4
-
-
46249132651
-
Modelling, analysis and implementation of an on-line video encoder
-
IEEE Computer Society
-
I. Assayad, Ph. Gemer, S. Yovine, and V. Bertin. Modelling, analysis and implementation of an on-line video encoder. In In DFMA '05. IEEE Computer Society, 2005.
-
(2005)
In DFMA '05
-
-
Assayad, I.1
Gemer, P.2
Yovine, S.3
Bertin, V.4
-
5
-
-
46249122912
-
-
Ismail Assayad and Sergio Yovine. P-ware: Performanceaware transaction-level simulation for network processor applications. Technical report, Verimag, Centre Équation, 38610 Gières, June 2006.
-
Ismail Assayad and Sergio Yovine. P-ware: Performanceaware transaction-level simulation for network processor applications. Technical report, Verimag, Centre Équation, 38610 Gières, June 2006.
-
-
-
-
6
-
-
0344951184
-
Metropolis: An integrated electronic system design environment
-
Felice Balarin, Yosinori Watanabe, Harry Hsieh, Luciano Lavagno, Claudio Passerone, and Alberto Sangiovanni-Vincentelli. Metropolis: An integrated electronic system design environment. Computer, 36(4):45-52, 2003.
-
(2003)
Computer
, vol.36
, Issue.4
, pp. 45-52
-
-
Balarin, F.1
Watanabe, Y.2
Hsieh, H.3
Lavagno, L.4
Passerone, C.5
Sangiovanni-Vincentelli, A.6
-
7
-
-
0036047772
-
Component-based design approach for multicore socs
-
New York, NY, USA, ACM Press
-
W. Cesario, A. Baghdadi, L. Gauthier, D. Lyonnard, G. Nicolescu, Y. Paviot, S. Yoo, A. A. Jerraya, and M. Diaz-Nava. Component-based design approach for multicore socs. In DAC '02: Proceedings of the 39th conference on Design automation, pages 789-794, New York, NY, USA, 2002. ACM Press.
-
(2002)
DAC '02: Proceedings of the 39th conference on Design automation
, pp. 789-794
-
-
Cesario, W.1
Baghdadi, A.2
Gauthier, L.3
Lyonnard, D.4
Nicolescu, G.5
Paviot, Y.6
Yoo, S.7
Jerraya, A.A.8
Diaz-Nava, M.9
-
8
-
-
84947240522
-
-
Radu Cornea, Nikil Dutt, Rajesh Gupta, Ingolf Krueger, Alex Nicolau, Doug Schmidt, and Sandeep Shukla. Forge: A framework for optimization of distributed embedded systems software. In IPDPS '03: Proceedings of the 17th International Symposium on Parallel and Distributed Processing, page 208.1, Washington, DC, USA, 2003. IEEE Computer Society.
-
Radu Cornea, Nikil Dutt, Rajesh Gupta, Ingolf Krueger, Alex Nicolau, Doug Schmidt, and Sandeep Shukla. Forge: A framework for optimization of distributed embedded systems software. In IPDPS '03: Proceedings of the 17th International Symposium on Parallel and Distributed Processing, page 208.1, Washington, DC, USA, 2003. IEEE Computer Society.
-
-
-
-
10
-
-
0035444259
-
Viper: A multiprocessor SOC for advanced set-top box and digital TV systems
-
Sept/Oct2001
-
Santanu Dutta, Rune Jensen, and Alf Rieckmann. Viper: A multiprocessor SOC for advanced set-top box and digital TV systems. IEEE Design and Test of Computers, 18(5):21-31, Sept/Oct2001.
-
IEEE Design and Test of Computers
, vol.18
, Issue.5
, pp. 21-31
-
-
Dutta, S.1
Jensen, R.2
Rieckmann, A.3
-
12
-
-
3042559894
-
Pipescompiler: A tool for instantiating application specific networks on chip
-
Antoine Jalabert, Srinivasan Murali, Luca Benini, and Giovanni De Micheli. Pipescompiler: A tool for instantiating application specific networks on chip. In DATE, pages 884-889, 2004.
-
(2004)
DATE
, pp. 884-889
-
-
Jalabert, A.1
Murali, S.2
Benini, L.3
Micheli, G.D.4
-
13
-
-
33646937706
-
ARTS: A system-level framework for modeling mpsoc components and analysis of their causality
-
IEEE Computer Society, sep
-
S. Mahadevan, M. Storgaard, J. Madsen, and K. M. Virk. ARTS: A system-level framework for modeling mpsoc components and analysis of their causality. In 13th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS). IEEE Computer Society, sep 2005.
-
(2005)
13th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS)
-
-
Mahadevan, S.1
Storgaard, M.2
Madsen, J.3
Virk, K.M.4
-
14
-
-
46249104582
-
-
Arno Moonen, Rene van den Berg, Marco Bekooij, Harpreet Bhullar, and Jef van Meerbergen. A multi-core architecture for in-car digital entertainment. In Proceedings of the GSPx conference, 2005.
-
Arno Moonen, Rene van den Berg, Marco Bekooij, Harpreet Bhullar, and Jef van Meerbergen. A multi-core architecture for in-car digital entertainment. In Proceedings of the GSPx conference, 2005.
-
-
-
-
15
-
-
33745209889
-
High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors
-
Joann M. Paul, Donald E. Thomas, and Andrew S. Cassidy. High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors. ACM Trans. Des. Autom. Electron. Syst., 10(3):431-461, 2005.
-
(2005)
ACM Trans. Des. Autom. Electron. Syst
, vol.10
, Issue.3
, pp. 431-461
-
-
Paul, J.M.1
Thomas, D.E.2
Cassidy, A.S.3
-
16
-
-
16244375583
-
Parallel programming models for a multi-processor soc platform applied to high-speed traffic management
-
New York, NY, USA, ACM Press
-
Pierre G. Paulin, Chuck Pilkington, Michel Langevin, Essaid Bensoudane, and Gabriela Nicolescu. Parallel programming models for a multi-processor soc platform applied to high-speed traffic management. In CODES+ISSS '04: Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, pages 48-53, New York, NY, USA, 2004. ACM Press.
-
(2004)
CODES+ISSS '04: Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
, pp. 48-53
-
-
Paulin, P.G.1
Pilkington, C.2
Langevin, M.3
Bensoudane, E.4
Nicolescu, G.5
-
18
-
-
16244362401
-
Modeling operation and microarchitcture concurrency for communication architectures with application to retargetable simulation
-
X. Zhu, W. Qin, and S. Malik. Modeling operation and microarchitcture concurrency for communication architectures with application to retargetable simulation. In ACM CODES+ISSS'04, 2004.
-
(2004)
ACM CODES+ISSS'04
-
-
Zhu, X.1
Qin, W.2
Malik, S.3
|