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Volumn 10, Issue 3, 2005, Pages 431-461

High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors

Author keywords

Computer aided design; Heterogeneous multiprocessors; Performance modeling; Schedulers; System modeling

Indexed keywords


EID: 33745209889     PISSN: 10844309     EISSN: 10844309     Source Type: Journal    
DOI: 10.1145/1080334.1080335     Document Type: Article
Times cited : (31)

References (28)
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    • Dijkstra, E.W.1
  • 10
    • 85008024835 scopus 로고    scopus 로고
    • Reuse: What's wrong with this picture?
    • GLASS, R. 1998. Reuse: What's wrong with this picture? IEEE Softw. 15, 2 (Mar.-Apr.), 57-59.
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    • Glass, R.1
  • 15
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    • A multilevel computing architecture for embedded multimedia applications
    • KARIM, F., MELLAN, A., NGUYEN, A., AYDONAT, U., AND ABDELRAHMAN, T. 2004. A multilevel computing architecture for embedded multimedia applications. IEEE Micro. 24, 3 (May-June), 56-66.
    • (2004) IEEE Micro. , vol.24 , Issue.3 MAY-JUNE , pp. 56-66
    • Karim, F.1    Mellan, A.2    Nguyen, A.3    Aydonat, U.4    Abdelrahman, T.5
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    • System timing
    • C. Mead, L. Conway. Eds. (Chapt. 7). Addison-Wesley, Reading, MA
    • SEITZ, C. L. 1980. System Timing. In Introduction to VLSI Systems. C. Mead, L. Conway. Eds. (Chapt. 7). Addison-Wesley, Reading, MA.
    • (1980) Introduction to VLSI Systems
    • Seitz, C.L.1
  • 24
    • 0032083545 scopus 로고    scopus 로고
    • Models and languages for parallel computing
    • SKILLICORN, D. AND TALIA, D. 1998. Models and languages for parallel computing. ACM Comput. Surv.30, 2 (June).
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    • SYSTEMC. Available at http://www.systemc.org/.
  • 27
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    • How many system architectures?
    • WOLF, W. 2003. How many system architectures? IEEE Comput. 36, 3 (Mar.), 93-95.
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    • Wolf, W.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.