Highly scalable and reliable multi-bit/cell nitride trapping nonvolatile memory using enhanced ANS-ONO process with a nitridized interface

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2006, Pages

  Shih, Y H ^a   Lai, E K ^a   Hsieh, J Y ^a   Hsu, T H ^a   Wu, M D ^a   Lu, C P ^a   Ni, K P ^a   Chou, T Y ^a   Yang, L W ^a   Hsieh, K Y ^a   Liaw, M H ^a   Lu, W P ^a   Chen, K C ^a   Ku, Joseph ^a   Ni, F L ^a   Liu, Rich ^a   Lu, Chih Yuan ^a  

^a MACRONIX INTERNATIONAL CO LTD   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON DEVICES;

BTBT-HH ERASE; NON-VOLATILE MEMORIES;

NITRIDES;

EID: 46049100055     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2006.346824     Document Type: Conference Paper

References (6)

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2. B. Eitan, G. Cohen, A. Shappir, E. Lusky, A. Givant, M. Janai, I. Bloom, Y. Polansky, "4-bit per Cell NROM Reliability", IEEE IEDM Technical Digest, pp. 547 - 550, 2005.
3. Y.H. Shih, S.C. Lee, H.T. Lue, M.D. Wu, T.H. Hsu, E.K. Lai, J.Y. Hsieh, C.W. Wu, L.W. Yang, K.Y. Hsieh, K.C. Chen, Rich Liu, and Chin-Yuan Lu, "Highly Reliable 2-bit/cell Nitride Trapping Flash Memory Using a Novel Array-Nitride-Sealing (ANS) ONO Process", IEEE IEDM Technical Digest, pp. 559 - 562, 2005.
4. L. Perniola, G. Iannaccone, B. De Salvo, G. Ghibaudo, G. Molas, C. Gerardi, S. Deleonibus, "Experimental and theoretical analysis of scaling issues in dual-bit discrete trap non-volatile memoryies", IEEE IEDM Technical Digest, pp. 877 - 880, 2005.
5. Tahui Wang, W.J. Tsai, S.H. Gu, C.T. Chan, C.C. Yeh, N.K. Zous, T.C. Lu, Sam Pan, and C.Y. Lu, "Reliability Models of Data Retention and Read-Disturb in 2-bit Nitride Storage Flash Memory Cells (Invited Paper)", IEEE IEDM Technical Digest, pp.169 - 172, 2003.
6. 2 during growth", Appl. Phys. Lett., vol. 35, no. 1, pp. 8 - 10, 1979.