Experimental and theoretical analysis of scaling issues in dual-bit discrete trap non-volatile memories

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 2005, Issue , 2005, Pages 857-860

  Perniola, L ^a,b,c   Iannaccone, G ^a   De Salvo, B ^b   Ghibaudo, G ^c   Molas, G ^b   Gerardi, C ^d   Deleonibus, S ^b  

^a UNIVERSITY OF PISA   (Italy)

^b CEA LETI   (France)

^c IMEP LAHC   (France)

^d STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COALESCENCE; NANOCRYSTALS; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON ON INSULATOR TECHNOLOGY;

DATA RETENTION; DUAL BIT READING; GATE LENGTHS; MEMORY CELLS;

NONVOLATILE STORAGE;

EID: 33847731449     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iedm.2005.1609492     Document Type: Conference Paper

References (7)

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3. B. De Salvo et. al., "How far will silicon nanocrystal push the scaling limit of NVMs technologies?", Tech. Dig of IEDM, pp. 597-600, 2003.
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7. E. Lusky et al., "Investigation of Channel Hot Electron injection by localized charge-trapping nonvolatile memory devices", IEEE Trans. on El. Dev., Vol. 51, No. 3, pp. 444-448, March 2004.