Electrical metrics for lithographic line-end tapering

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 7028, Issue , 2008, Pages

  Gupta, Puneet ^c   Jeong, Kwangok ^a   Kahng, Andrew B ^a,b   Park, Chul Hong ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

GATE EDGE; LAYOUT AREA; LINE ENDS; LOW K1 LITHOGRAPHY; MASK TECHNOLOGY; METRICS (CO); NEXT-GENERATION LITHOGRAPHY (NGL); PHOTO MASKING;

CADMIUM; CADMIUM COMPOUNDS; COMPUTER NETWORKS; TECHNOLOGY;

LITHOGRAPHY;

EID: 45549091504     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.793117     Document Type: Conference Paper

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