Double exposure double etch for dense SRAM: A designer's dream

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6924, Issue , 2008, Pages

  Sarma, Chandra ^a   Gabor, Allen ^b   Halle, Scott ^b   Haffner, Henning ^a   Herold, Klaus ^a   Tsou, Len ^b   Wang, Helen ^b   Zhuang, Haoren ^a  

^a INFINEON TECHNOLOGIES   (United States)

^b IBM MICROELECTRONICS   (United States)

Author keywords

DE2; Double patterning; Gate process window; Printed assist feature; SRAF; SRAM

Indexed keywords

AEROSPACE APPLICATIONS; ARCHITECTURAL DESIGN; CELLS; CURVE FITTING; DESIGN; FUZZY LOGIC; LITHOGRAPHY; LOGIC DEVICES; NANOTECHNOLOGY; OPTICAL CORRELATION; OPTIMIZATION; PROCESS DESIGN; PROCESS ENGINEERING; RANDOM PROCESSES; SPONTANEOUS EMISSION; WINDOWS;

(E ,3E) PROCESS; 45NM NODE; ACTIVE AREAS; COST OF OWNERSHIP (COO); DESIGN RULES; DEVICE PERFORMANCES; DOUBLE EXPOSURE; DOUBLE PATTERNING; ELECTRICAL RESULTS; FULLY INTEGRATED; GATE LINE; HIGH YIELDING; INTEGRATION SCHEMES; LITHOGRAPHIC PROCESSING; LITHOGRAPHY PROCESSES; LOW LEAKAGE; ON-WAFER; OPTICAL MICRO LITHOGRAPHY; PATTERNING PROCESSES; PROCESS WINDOW OPTIMIZATION; PROCESS WINDOWS; SINGLE ETCH; SINGLE EXPOSURE; SRAM ARRAYS; SRAM CELLS; SUSTAINABLE MANUFACTURING;

STATIC RANDOM ACCESS STORAGE;

EID: 45449097061     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.772985     Document Type: Conference Paper

References (5)

1. C. Sarma et al., "Finding the right way: DFM vs. area efficiency for 65nm gate layer lithography", Optical Microlithography XIX, Proc. Of SPIE Vol. 6154 6154IL-1, 2006
2. H. Zhuang, H. Wang, C. Yap, A. Gutmann, J. Lian, C. Sarma, L. Tsou, A. Gabor, U. Schroeder, S. Halle, K. Herold, H. Haffner, H. Lee, N. Rovedo, C. Chang, H. Ng, D. Shum, R. Wise, M. Hierlemann, and M. Ieong: "Patterning strategies for gate level tip-tip distance reduction in SRAM cell for 45nm and beyond", Semiconductor Technology ISTC 2007, Proc. Vol. 2007-01, 154-159 (2007).
3. J. Meiring, H. Haffner, C. Fonseca, S. Halle, and S. Mansfield: "ACLV Driven Double-Patterning Decomposition With Extensively Added Printing Assist Features (PrAFs)", Proc. SPIE Vol. 6520 (SPIE, Bellingham, WA, 2007) 65201U.
4. H. Haffner, J. Meiring, Z. Baum, S. Halle: "Paving the way to a full chip gate level double patterning application", Proc. SPIE Vol. 6730 (SPIE, Bellingham, WA, 2007) 67302C.
5. H. Haffner, J. Meiring, Z. Baum, S. Halle, and S. Mansfield, "Solving the gate level ACLV challenge with double patterning and printing assist features", Microlithography World, in press.