Strained silicon-on-insulator - Fabrication and characterization

ECS Transactions

Volumn 6, Issue 4, 2007, Pages 339-344

  Reiche, M ^a   Himcinschi, C ^a   Gosele U ^a   Christiansen, S ^a   Mantl, S ^b   Buca, D ^b   Zhao, Q T ^b   Feste, S ^b   Loo, R ^c   Nguyen, D ^c   Buchholtz, W ^d   Wei, A ^d   Horstmann, M ^d   Feijoo, D ^e   Storck, P ^e  

^a MAX PLANCK INSTITUTE OF MICROSTRUCTURE PHYSICS   (Germany)

^b FORSCHUNGSZENTRUM JÜLICH   (Germany)

^c IMEC   (Belgium)

^d IBM MICROELECTRONICS   (United States)

^e SILTRONIC AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER LAYERS; ELECTRON MOBILITY; FABRICATION; SI-GE ALLOYS; SILICON COMPOUNDS; SILICON WAFERS; STRAINED SILICON; SUBSTRATES; WAFER BONDING;

DRIVE CURRENTS; FABRICATION AND CHARACTERIZATIONS; LAYER TRANSFER PROCESS; LONG CHANNEL DEVICES; PROCESS COSTS; SIGE BUFFER LAYER; STRAINED-SI; STRAINED-SOI;

SILICON ON INSULATOR TECHNOLOGY;

EID: 45449090851     PISSN: 19385862     EISSN: 19386737     Source Type: Conference Proceeding    
DOI: 10.1149/1.2728880     Document Type: Conference Paper

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